Issued Patents All Time
Showing 26–50 of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11211114 | Memories and memory components with interconnected and redundant data interfaces | Frederick A. Ware, Ely Tsern, John Eric Linstadt, Scott C. Best, Kenneth L. Wright | 2021-12-28 |
| 11184197 | Burst-tolerant decision feedback equalization | Abhijit Abhyankar | 2021-11-23 |
| 11127444 | Signal receiver with skew-tolerant strobe gating | Andrew M. Fuller, Robert E. Palmer, Michael D. Bucher, Thoai-Thai Le | 2021-09-21 |
| 11068161 | Memory module with emulated memory device population | Catherine Chen, John Eric Linstadt | 2021-07-20 |
| 11016837 | Memory module register access | Catherine Chen, Scott C. Best, John Eric Linstadt, Frederick A. Ware | 2021-05-25 |
| 11003601 | Memory system design using buffer(s) on a mother board | Chi-Ming Yeung, Yoshie Nakabayashi, Henry Stracovsky | 2021-05-11 |
| 10970240 | Protocol including a command-specified timing reference signal | Ian Shaeffer | 2021-04-06 |
| 10846252 | Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules | Frederick A. Ware, Ely Tsern, John Eric Linstadt, Kenneth L. Wright | 2020-11-24 |
| 10789185 | Memory modules and systems with variable-width data ranks and configurable data-rank timing | John Eric Linstadt, Catherine Chen | 2020-09-29 |
| 10613995 | Training and operations with a double buffered memory topology | Chi-Ming Yeung, Yoshie Nakabayashi, Henry Stracovsky | 2020-04-07 |
| 10614002 | Memory system design using buffer(S) on a mother board | Chi-Ming Yeung, Yoshie Nakabayashi, Henry Stracovsky | 2020-04-07 |
| 10607670 | Memory components and controllers that calibrate multiphase synchronous timing references | Scott C. Best, Lei Luo, Ian Shaeffer | 2020-03-31 |
| 10607685 | Method and apparatus for calibrating write timing in a memory system | Alok Gupta, Ian Shaeffer, Steven C. Woo | 2020-03-31 |
| 10360972 | Memories and memory components with interconnected and redundant data interfaces | Frederick A. Ware, Ely Tsern, John Eric Linstadt, Scott C. Best, Kenneth L. Wright | 2019-07-23 |
| 10331587 | Memory controller that uses a specific timing reference signal in connection with a data burst following a specified idle period | Ian Shaeffer | 2019-06-25 |
| 10320591 | Burst-tolerant decision feedback equalization | Abhijit Abhyankar | 2019-06-11 |
| 10304517 | Method and apparatus for calibrating write timing in a memory system | Alok Gupta, Ian Shaeffer, Steven C. Woo | 2019-05-28 |
| 10223309 | Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules | Frederick A. Ware, Ely Tsern, John Eric Linstadt, Kenneth L. Wright | 2019-03-05 |
| 10169258 | Memory system design using buffer(s) on a mother board | Chi-Ming Yeung, Yoshie Nakabayashi, Henry Stracovsky | 2019-01-01 |
| 10146608 | Memory module register access | Catherine Chen, Scott C. Best, John Eric Linstadt, Frederick A. Ware | 2018-12-04 |
| 10109324 | Extended capacity memory module with dynamic data buffers | John Eric Linstadt | 2018-10-23 |
| 9916873 | Extended capacity memory module with dynamic data buffers | John Eric Linstadt | 2018-03-13 |
| 9881662 | Method and apparatus for calibrating write timing in a memory system | Alok Gupta, Ian Shaeffer, Steven C. Woo | 2018-01-30 |
| 9824730 | Memory components and controllers that calibrate multiphase synchronous timing references | Scott C. Best, Lei Luo, Ian Shaeffer | 2017-11-21 |
| 9665507 | Protocol including a command-specified timing reference signal | Ian Shaeffer | 2017-05-30 |