Issued Patents All Time
Showing 25 most recent of 234 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12395173 | Integrated circuit that applies different data interface terminations during and after write data reception | Kyung Suk Oh | 2025-08-19 |
| 12394471 | Memory system topologies including a memory die stack | Ely Tsern, Craig E. Hampel | 2025-08-19 |
| 12386763 | Protocol including selective output by memory of a timing reference signal | Thomas J. Giovannini | 2025-08-12 |
| 12347479 | Command-triggered data clock distribution mode | Lei Luo, Liji Gopalakrishnan | 2025-07-01 |
| 12301227 | On-die termination | — | 2025-05-13 |
| 12298848 | Memory error detection | Craig E. Hampel | 2025-05-13 |
| 12298920 | Memory access during memory calibration | Frederick A. Ware | 2025-05-13 |
| 12249399 | On-die termination of address and command signals | Kyung Suk Oh | 2025-03-11 |
| 12249392 | Memory controller with staggered request signal output | Bret G. Stott, Benedict Lau | 2025-03-11 |
| 12189548 | Buffer IC with asymmetric memory module interfaces | Arun Vaidyanath, Sanku Mukherjee | 2025-01-07 |
| 12190990 | Deferred fractional memory row activation | James E. Harris, Thomas Vogelsang, Frederick A. Ware | 2025-01-07 |
| 12147367 | Folded memory modules | Amir Amirkhany, Suresh Rajan, Ravindranath Kollipara, David A. Secker | 2024-11-19 |
| 12142348 | Memory device comprising programmable command-and-address and/or data interfaces | Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson, Akash Bansal +2 more | 2024-11-12 |
| 12136452 | Method and apparatus for calibrating write timing in a memory system | Thomas J. Giovannini, Alok Gupta, Steven C. Woo | 2024-11-05 |
| 12066958 | Clock generation for timing communications with ranks of memory devices | Jared L. Zerbe, John Eble | 2024-08-20 |
| 12055984 | Computer in an input device | Michael E. Leclerc, Brett W. Degner | 2024-08-06 |
| 12002540 | On-die termination of address and command signals | Kyung Suk Oh | 2024-06-04 |
| 11955161 | Command-triggered data clock distribution mode | Lei Luo, Liji Gopalakrishnan | 2024-04-09 |
| 11947468 | Memory access during memory calibration | Frederick A. Ware | 2024-04-02 |
| 11928020 | Memory error detection | Craig E. Hampel | 2024-03-12 |
| 11830573 | Memory controller with staggered request signal output | Bret G. Stott, Benedict Lau | 2023-11-28 |
| 11816047 | Protocol including a command-specified timing reference signal | Thomas J. Giovannini | 2023-11-14 |
| 11804250 | Memory with deferred fractional row activation | James E. Harris, Thomas Vogelsang, Frederick A. Ware | 2023-10-31 |
| 11790962 | Strobe acquisition and tracking | Bret G. Stott, Frederick A. Ware, Yuanlong Wang | 2023-10-17 |
| 11782863 | Memory module with configurable command buffer | Liji Gopalakrishnan, Yi Lu | 2023-10-10 |