Issued Patents All Time
Showing 26–50 of 234 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11782863 | Memory module with configurable command buffer | Liji Gopalakrishnan, Yi Lu | 2023-10-10 |
| 11755521 | Folded memory modules | Amir Amirkhany, Suresh Rajan, Ravindranath Kollipara, David A. Secker | 2023-09-12 |
| 11742855 | On-die termination | — | 2023-08-29 |
| 11741041 | Interface bus resource allocation | Eric C. Gaertner, John T. Orchard, Michael Murphy, Ronald P. Songco, Corey N. Axelowitz +1 more | 2023-08-29 |
| 11727982 | Memory system topologies including a memory die stack | Ely Tsern, Craig E. Hampel | 2023-08-15 |
| 11688441 | On-die termination of address and command signals | Kyung Suk Oh | 2023-06-27 |
| 11682448 | Method and apparatus for calibrating write timing in a memory system | Thomas J. Giovannini, Alok Gupta, Steven C. Woo | 2023-06-20 |
| 11651823 | Fractional program commands for memory devices | Brent Haukness, Gary B. Bronner | 2023-05-16 |
| 11636801 | Computer console for throttling the video bitrate of video streams to interface with an electronic device | Reese A. Schreiber, Carlos Calderon, Collin L. Pieper, Jeffrey R. Wilcox, Robert L. Ridenour | 2023-04-25 |
| 11630788 | Clock generation for timing communications with ranks of memory devices | Jared L. Zerbe, John Eble | 2023-04-18 |
| 11587605 | Command-triggered data clock distribution | Lei Luo, Liji Gopalakrishnan | 2023-02-21 |
| 11579965 | Memory error detection | Craig E. Hampel | 2023-02-14 |
| 11474957 | Memory access during memory calibration | Frederick A. Ware | 2022-10-18 |
| 11468928 | On-die termination of address and command signals | Kyung Suk Oh | 2022-10-11 |
| 11409682 | Folded memory modules | Amir Amirkhany, Suresh Rajan, Ravindranath Kollipara, David A. Secker | 2022-08-09 |
| 11404103 | Method and apparatus for calibrating write timing in a memory system | Thomas J. Giovannini, Alok Gupta, Steven C. Woo | 2022-08-02 |
| 11372795 | Memory with alternative command interfaces | Liji Gopalakrishnan, Yi Lu | 2022-06-28 |
| 11349478 | Integrated circuit that applies different data interface terminations during and after write data reception | Kyung Suk Oh | 2022-05-31 |
| 11341067 | Coordinating memory operations using memory-device-generated reference signals | Scott C. Best | 2022-05-24 |
| 11328764 | Memory system topologies including a memory die stack | Ely Tsern, Craig E. Hampel | 2022-05-10 |
| 11302371 | Memory systems and methods for dividing physical memory locations into temporal memory locations | — | 2022-04-12 |
| 11302368 | Memory device with circuitry to transmit feedback indicative of a phase relationship | Bret G. Stott, Benedict Lau | 2022-04-12 |
| 11289139 | Memory components and controllers that calibrate multiphase synchronous timing references | Thomas J. Giovannini, Scott C. Best, Lei Luo | 2022-03-29 |
| 11270741 | Deferred fractional memory row activation | James E. Harris, Thomas Vogelsang, Frederick A. Ware | 2022-03-08 |
| 11211105 | Memory device comprising programmable command-and-address and/or data interfaces | Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson, Akash Bansal +2 more | 2021-12-28 |