Issued Patents All Time
Showing 25 most recent of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11113204 | Translation invalidation in a translation cache serving an accelerator | Bartholomew Blaner, Michael S. Siegel, Jeffrey A. Stuecheli, William J. Starke, Kenneth M. Valk +1 more | 2021-09-07 |
| 11030110 | Integrated circuit and data processing system supporting address aliasing in an accelerator | Michael S. Siegel, Bartholomew Blaner, Jeffrey A. Stuecheli, William J. Starke, Derek E. Williams +2 more | 2021-06-08 |
| 10846235 | Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator | Bartholomew Blaner, Michael S. Siegel, Jeffrey A. Stuecheli, William J. Starke, Kenneth M. Valk +1 more | 2020-11-24 |
| 10761995 | Integrated circuit and data processing system having a configurable cache directory for an accelerator | Bartholomew Blaner, Jeffrey A. Stuecheli, Michael S. Siegel, William J. Starke, Curtis C. Wollbrink +2 more | 2020-09-01 |
| 10613979 | Accelerator memory coherency with single state machine | Kenneth M. Valk, Guy L. Guthrie, Derek E. Williams, Michael S. Siegel | 2020-04-07 |
| 10528399 | Techniques for faster loading of data for accelerators | Mark S. Fredrickson, John Michael Borkenhagen, Michael A. Muston, Spencer K. Millican | 2020-01-07 |
| 10216653 | Pre-transmission data reordering for a serial interface | Lakshminarayana B. Arimilli, Yiftach Benjamini, Bartholomew Blaner, Daniel M. Dreps, David J. Krolak +6 more | 2019-02-26 |
| 9778933 | Non-serialized push instruction for pushing a message payload from a sending thread to a receiving thread | Lakshminarayana B. Arimilli, Bernard C. Drerup, Guy L. Guthrie, William J. Starke, Jeffrey A. Stuecheli | 2017-10-03 |
| 9766890 | Non-serialized push instruction for pushing a message payload from a sending thread to a receiving thread | Lakshminarayana B. Arimilli, Bernard C. Drerup, Guy L. Guthrie, William J. Starke, Jeffrey A. Stuecheli | 2017-09-19 |
| 9684551 | Addressing for inter-thread push communication | Lakshminarayana B. Arimilli, William J. Starke, Randal C. Swanberg | 2017-06-20 |
| 9678812 | Addressing for inter-thread push communication | Lakshminarayana B. Arimilli, William J. Starke, Randal C. Swanberg | 2017-06-13 |
| 9575825 | Push instruction for pushing a message payload from a sending thread to a receiving thread | Lakshminarayana B. Arimilli, Bernard C. Drerup, Bradly G. Frey, Guy L. Guthrie, William J. Starke +1 more | 2017-02-21 |
| 9569293 | Push instruction for pushing a message payload from a sending thread to a receiving thread | Lakshminarayana B. Arimilli, Bernard C. Drerup, Bradly G. Frey, Guy L. Guthrie, William J. Starke +1 more | 2017-02-14 |
| 9342387 | Hardware-assisted interthread push communication | Lakshminarayana B. Arimilli, Bernard C. Drerup, Charles F. Marino, William J. Starke | 2016-05-17 |
| 9286148 | Hardware-assisted interthread push communication | Lakshminarayana B. Arimilli, Bernard C. Drerup, Charles F. Marino, William J. Starke | 2016-03-15 |
| 8792332 | Implementing lane shuffle for fault-tolerant communication links | Ryan Abel Heckendorf, Kerry Christopher Imming, Ibrahim Abdel-Rahman Ouda | 2014-07-29 |
| 8589630 | Methods and apparatus for handling a cache miss | Chad B. McBride, Andrew Henry Wottreng | 2013-11-19 |
| 8490102 | Resource allocation management using IOC token requestor logic | Glen Howard Handlogten | 2013-07-16 |
| 8327075 | Methods and apparatus for handling a cache miss | Chad B. McBride, Andrew Henry Wottreng | 2012-12-04 |
| 8170024 | Implementing pointer and stake model for frame alteration code in a network processor | Kerry Christopher Imming, Joseph Franklin Logan, Tolga Ozguner, Michael S. Siegel | 2012-05-01 |
| 8127082 | Method and apparatus for allowing uninterrupted address translations while performing address translation cache invalidates and other cache operations | Chad B. McBride, Andrew Henry Wottreng | 2012-02-28 |
| 7961732 | Method and hardware apparatus for implementing frame alteration commands | Ibrahim Abdel-Rahman Ouda, James A. Steenburgh, Jason Andrew Thompson | 2011-06-14 |
| 7917700 | Method and cache control circuit for replacing cache lines using alternate PLRU algorithm and victim cache coherency state | Chad B. McBride, Jack Chris Randolph | 2011-03-29 |
| 7840744 | Rank select operation between an XIO interface and a double data rate interface | Mark David Bellows, Kent Harold Haselhorst, David Alan Norgaard | 2010-11-23 |
| 7809008 | Methods and apparatus for routing packets | Ibrahim Abdel-Rahman Ouda, James A. Steenburgh, Jason Andrew Thompson | 2010-10-05 |