BB

Bartholomew Blaner

IBM: 103 patents #529 of 70,183Top 1%
Globalfoundries: 2 patents #1,397 of 4,424Top 35%
Overall (All Time): #12,952 of 4,157,543Top 1%
106
Patents All Time

Issued Patents All Time

Showing 25 most recent of 106 patents

Patent #TitleCo-InventorsDate
11573896 DRAM caching storage class memory Bulent Abali, Alper Buyuktosunoglu, William J. Starke 2023-02-07
11221957 Promotion of ERAT cache entries Jay G. Heaslip, Benjamin Herrenschmidt, Robert D. Herzl, Jody B. Joyner, Jon K. Kriegel +1 more 2022-01-11
11113204 Translation invalidation in a translation cache serving an accelerator Michael S. Siegel, Jeffrey A. Stuecheli, William J. Starke, Kenneth M. Valk, John D. Irish +1 more 2021-09-07
11030110 Integrated circuit and data processing system supporting address aliasing in an accelerator Michael S. Siegel, Jeffrey A. Stuecheli, William J. Starke, Derek E. Williams, Kenneth M. Valk +2 more 2021-06-08
10936402 Speculative data processing and recovery Bulent Abali, John J. Reilly 2021-03-02
10884943 Speculative checkin of ERAT cache entries Jay G. Heaslip, Robert D. Herzl, Jody B. Joyner, Jeffrey A. Stuecheli 2021-01-05
10846235 Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator Michael S. Siegel, Jeffrey A. Stuecheli, William J. Starke, Kenneth M. Valk, John D. Irish +1 more 2020-11-24
10831593 Live partition mobility enabled hardware accelerator address translation fault resolution Lakshminarayana B. Arimilli, Richard Louis Arndt 2020-11-10
10824585 Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elements Ganesh Balakrishnan, John J. Reilly, Jeffrey A. Stuecheli 2020-11-03
10824952 Reconfigurable array processor for pattern matching Bulent Abali, Ganesh Balakrishnan, Peter A. Sandon, Jeffrey A. Stuecheli 2020-11-03
10824953 Reconfigurable array processor for pattern matching Bulent Abali, Ganesh Balakrishnan, Peter A. Sandon, Jeffrey A. Stuecheli 2020-11-03
10817491 Efficient and accurate lookups of data by a stream processor using a hash table Bulent Abali, John J. Reilly 2020-10-27
10803040 Efficient and accurate lookups of data by a stream processor using a hash table Bulent Abali, John J. Reilly 2020-10-13
10761995 Integrated circuit and data processing system having a configurable cache directory for an accelerator Jeffrey A. Stuecheli, Michael S. Siegel, William J. Starke, Curtis C. Wollbrink, Kenneth M. Valk +2 more 2020-09-01
10698812 Updating cache using two bloom filters Michael Bar-Joshua, Yiftach Benjamini, Michael Grubman 2020-06-30
10599569 Maintaining consistency between address translations in a data processing system Jay G. Heaslip, Robert D. Herzl, Jody B. Joyner 2020-03-24
10585744 Managed hardware accelerator address translation fault resolution utilizing a credit Lakshminarayana B. Arimilli, Richard Louis Arndt 2020-03-10
10572381 Updating cache using two bloom filters Michael Bar-Joshua, Yiftach Benjamini, Michael Grubman 2020-02-25
10572337 Live partition mobility enabled hardware accelerator address translation fault resolution Lakshminarayana B. Arimilli, Richard Louis Arndt 2020-02-25
10565102 Updating cache using two bloom filters Michael Bar-Joshua, Yiftach Benjamini, Michael Grubman 2020-02-18
10552313 Updating cache using two bloom filters Michael Bar-Joshua, Yiftach Benjamini, Michael Grubman 2020-02-04
10545816 Managed hardware accelerator address translation fault resolution utilizing a credit Lakshminarayana B. Arimilli, Richard Louis Arndt 2020-01-28
10528418 Hardware accelerator address translation fault resolution Lakshminarayana B. Arimilli, Richard Louis Arndt 2020-01-07
10394711 Managing lowest point of coherency (LPC) memory using a service layer adapter Etai Adar, Lakshminarayana B. Arimilli, Yiftach Benjamini, William J. Starke, Jeffrey A. Stuecheli 2019-08-27
10380048 Suspend and resume in a time shared coprocessor Bulent Abali, Craig B. Agricola, Kenneth A. Lauricella, John J. Reilly, Dorothy Marie Thelen 2019-08-13