Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11734188 | Unified translation miss queue for multiple address translation modes | Charles D. Wait, David Campbell, Jake Truelove, Jody B. Joyner, Glenn O. Kincaid | 2023-08-22 |
| 11636043 | Sleeping and waking-up address translation that conflicts with translation level of active page table walks | Charles D. Wait, Jake Truelove, David Campbell, Jody B. Joyner, Glenn O. Kincaid | 2023-04-25 |
| 11556475 | Power optimized prefetching in set-associative translation lookaside buffer structure | David Campbell, George W. Rohrbaugh, III, Jake Truelove, Charles D. Wait, Jody B. Joyner | 2023-01-17 |
| 11422947 | Determining page size via page table cache | David Campbell, Jake Truelove, Charles D. Wait | 2022-08-23 |
| 11221957 | Promotion of ERAT cache entries | Bartholomew Blaner, Jay G. Heaslip, Benjamin Herrenschmidt, Robert D. Herzl, Jody B. Joyner +1 more | 2022-01-11 |
| 10380031 | Ensuring forward progress for nested translations in a memory management unit | Guy L. Guthrie, Jody B. Joyner, Bradley Nelson, Charles D. Wait | 2019-08-13 |
| 10318435 | Ensuring forward progress for nested translations in a memory management unit | Guy L. Guthrie, Jody B. Joyner, Bradley Nelson, Charles D. Wait | 2019-06-11 |
| 8856490 | Optimizing TLB entries for mixed page size storage in contiguous memory | Dong Chen, Alan Gara, Mark E. Giampapa, Philip Heidelberger, Martin Ohmacht +1 more | 2014-10-07 |
| 8826299 | Spawned message state determination | Mark G. Kupferschmidt, Paul E. Schardt | 2014-09-02 |
| 8726295 | Network on chip with an I/O accelerator | Russell D. Hoover, Eric O. Mejdrich | 2014-05-13 |
| 8688953 | Method and apparatus for managing software controlled cache of translating the physical memory access of a virtual machine between different levels of translation entities | Hubertus Franke, Benjamin Herrenschmidt, Andrew M. Theurer, James Xenidis | 2014-04-01 |
| 8490110 | Network on chip with a low latency, high bandwidth application messaging interconnect | Russell D. Hoover, Eric O. Mejdrich, Robert A. Shearer | 2013-07-16 |
| 8438578 | Network on chip with an I/O accelerator | Russell D. Hoover, Eric O. Mejdrich | 2013-05-07 |
| 8429377 | Optimizing TLB entries for mixed page size storage in contiguous memory | Dong Chen, Alan Gara, Mark E. Giampapa, Philip Heidelberger, Martin Ohmacht +1 more | 2013-04-23 |
| 8296547 | Loading entries into a TLB in hardware via indirect TLB entries | Timothy H. Heil, Benjamin Herrenschmidt, Paul Mackerras, Andrew Henry Wottreng | 2012-10-23 |
| 8275971 | Method and apparatus for managing software controlled cache of translating the physical memory access of a virtual machine between different levels of translation entities | Hubertus Franke, Benjamin Herrenschmidt, Andrew M. Theurer, James Xenidis | 2012-09-25 |
| 8230179 | Administering non-cacheable memory load instructions | Jamie R. Kuesel | 2012-07-24 |
| 8205067 | Context switching and synchronization | Eric O. Mejdrich | 2012-06-19 |
| 7913010 | Network on chip with a low latency, high bandwidth application messaging interconnect | Russell D. Hoover, Eric O. Mejdrich | 2011-03-22 |
| 7840757 | Method and apparatus for providing high speed memory for a processing unit | Bruce Beukema, Russell D. Hoover, Jamie R. Kuesel, Eric O. Mejdrich, Robert A. Shearer +1 more | 2010-11-23 |
| 7818503 | Method and apparatus for memory utilization | Russell D. Hoover, Eric O. Mejdrich, Robert A. Shearer | 2010-10-19 |
| 7752413 | Method and apparatus for communicating between threads | Russell D. Hoover, Eric O. Mejdrich, Robert A. Shearer | 2010-07-06 |
| 7681020 | Context switching and synchronization | Eric O. Mejdrich | 2010-03-16 |
| 7577794 | Low latency coherency protocol for a multi-chip multiprocessor system | Bruce Beukema, Russell D. Hoover, Eric O. Mejdrich, Sandra S. Woodward | 2009-08-18 |
| 7552236 | Routing interrupts in a multi-node system | Todd A. Greenfield | 2009-06-23 |