Issued Patents All Time
Showing 1–25 of 71 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11455011 | Modular computing device with common AC power | Peter Atkinson, James Hunter, Eric O. Mejdrich, Jay Tsao, Gregory M. Daly +1 more | 2022-09-27 |
| 9495498 | Universal inter-layer interconnect for multi-layer semiconductor stacks | Gerald K. Bartley, Charles L. Johnson, Steven Paul VanderWiel, Patrick R. Varekamp | 2016-11-15 |
| 9092347 | Allocating cache for use as a dedicated local storage | Miguel Comparan, Robert A. Shearer, Alfred T. Watson, III | 2015-07-28 |
| 9053037 | Allocating cache for use as a dedicated local storage | Miguel Comparan, Robert A. Shearer, Alfred T. Watson, III | 2015-06-09 |
| 9041713 | Dynamic spatial index remapping for optimal aggregate performance | Jeffrey Douglas Brown, Eric O. Mejdrich, Robert A. Shearer | 2015-05-26 |
| 9021237 | Low latency variable transfer network communicating variable written to source processing core variable register allocated to destination thread to destination processing core variable register allocated to source thread | Miguel Comparan, Robert A. Shearer, Alfred T. Watson, III | 2015-04-28 |
| 8983891 | Pattern matching engine for use in a pattern matching accelerator | Giora Biran, Christoph Hagleitner, Timothy H. Heil, Jan Van Lunteren | 2015-03-17 |
| 8966182 | Software and hardware managed dual rule bank cache for use in a pattern matching accelerator | Giora Biran, Christoph Hagleitner, Timothy H. Heil, Jan Van Lunteren | 2015-02-24 |
| 8954973 | Transferring architected state between cores | Miguel Comparan, Robert A. Shearer, Alfred T. Watson, III | 2015-02-10 |
| 8949836 | Transferring architected state between cores | Miguel Comparan, Robert A. Shearer, Alfred T. Watson, III | 2015-02-03 |
| 8799188 | Algorithm engine for use in a pattern matching accelerator | Giora Biran, Christoph Hagleitner, Timothy H. Heil, Jan Van Lunteren | 2014-08-05 |
| 8773449 | Rendering of stereoscopic images with multithreaded rendering software pipeline | Eric O. Mejdrich, Paul E. Schardt, Robert A. Shearer | 2014-07-08 |
| 8736068 | Hybrid bonding techniques for multi-layer semiconductor stacks | Gerald K. Bartley, Charles L. Johnson, Steven Paul VanderWiel | 2014-05-27 |
| 8726295 | Network on chip with an I/O accelerator | Jon K. Kriegel, Eric O. Mejdrich | 2014-05-13 |
| 8572324 | Network on chip with caching restrictions for pages of computer memory | Eric O. Mejdrich | 2013-10-29 |
| 8526422 | Network on chip with partitions | Eric O. Mejdrich, Paul E. Schardt, Robert A. Shearer | 2013-09-03 |
| 8493398 | Dynamic data type aligned cache optimized for misaligned packed structures | Miguel Comparan, Eric O. Mejdrich | 2013-07-23 |
| 8490110 | Network on chip with a low latency, high bandwidth application messaging interconnect | Jon K. Kriegel, Eric O. Mejdrich, Robert A. Shearer | 2013-07-16 |
| 8489787 | Sharing sampled instruction address registers for efficient instruction sampling in massively multithreaded processors | Etai Adar, Srinivasan Ramani, Eric F. Robinson, Thuong Quang Truong | 2013-07-16 |
| 8478736 | Pattern matching accelerator | Giora Biran, Christoph Hagleitner, Timothy H. Heil, Jan Van Lunteren | 2013-07-02 |
| 8445918 | Thermal enhancement for multi-layer semiconductor stacks | Gerald K. Bartley, Charles L. Johnson, Steven Paul VanderWiel | 2013-05-21 |
| 8438578 | Network on chip with an I/O accelerator | Jon K. Kriegel, Eric O. Mejdrich | 2013-05-07 |
| 8392664 | Network on chip | Miguel Comparan, Eric O. Mejdrich | 2013-03-05 |
| 8330489 | Universal inter-layer interconnect for multi-layer semiconductor stacks | Gerald K. Bartley, Charles L. Johnson, Steven Paul VanderWiel, Patrick R. Varekamp | 2012-12-11 |
| 8332592 | Graphics processor with snoop filter | Eric O. Mejdrich | 2012-12-11 |