| 12048256 |
Interfacing with superconducting circuitry |
Adam J. Muff, Indranil S. Sen, Paul D. Berndt |
2024-07-23 |
$294,758,000 |
| 11218139 |
Test and characterization of ring in superconducting domain through built-in self-test |
Clint Wayne Mumford, Kshitiz Saxena, Adam J. Muff, Oscar Rosell |
2022-01-04 |
$89,531,000 |
| 10831504 |
Processor with hybrid pipeline capable of operating in out-of-order and in-order modes |
Andrew D. Hilton, Hans M. Jacobson, Brian M. Rogers, Robert A. Shearer, Ken V. Vu +1 more |
2020-11-10 |
$848,000 |
| 10672368 |
No miss cache structure for real-time image transformations with multiple LSR processing engines |
Ryan Scott Haraden, Tolga Ozguner, Adam J. Muff, Jeffrey Powers Bradford, Christopher Jon Johnson +1 more |
2020-06-02 |
$84,040,000 |
| 10514753 |
Selectively applying reprojection processing to multi-layer scenes for optimizing late stage reprojection power |
Ryan Scott Haraden, Jeffrey Powers Bradford, Adam J. Muff, Gene Leung, Tolga Ozguner |
2019-12-24 |
$81,103,000 |
| 10410349 |
Selective application of reprojection processing on layer sub-regions for optimizing late stage reprojection power |
Ryan Scott Haraden, Jeffrey Powers Bradford, Adam J. Muff, Gene Leung, Tolga Ozguner |
2019-09-10 |
$58,792,000 |
| 10403029 |
Methods and systems for multistage post-rendering image transformation |
Tolga Ozguner, Ryan Scott Haraden, Jeffrey Powers Bradford |
2019-09-03 |
$68,397,000 |
| 10360832 |
Post-rendering image transformation using parallel image transformation pipelines |
Tolga Ozguner, Christopher Jon Johnson, Jeffrey Powers Bradford |
2019-07-23 |
$89,396,000 |
| 10338816 |
Reducing negative effects of insufficient data throughput for real-time processing |
Tolga Ozguner, Ishan Jitendra Bhatt, Ryan Scott Haraden, Jeffrey Powers Bradford, Gene Leung |
2019-07-02 |
$68,442,000 |
| 10255891 |
No miss cache structure for real-time image transformations with multiple LSR processing engines |
Ryan Scott Haraden, Tolga Ozguner, Adam J. Muff, Jeffrey Powers Bradford, Christopher Jon Johnson +1 more |
2019-04-09 |
$61,620,000 |
| 10242654 |
No miss cache structure for real-time image transformations |
Tolga Ozguner, Jeffrey Powers Bradford, Gene Leung, Adam J. Muff, Ryan Scott Haraden +1 more |
2019-03-26 |
$49,304,000 |
| 10241470 |
No miss cache structure for real-time image transformations with data compression |
Tolga Ozguner, Gene Leung, Jeffrey Powers Bradford, Adam J. Muff, Ryan Scott Haraden +1 more |
2019-03-26 |
$49,304,000 |
| 10114652 |
Processor with hybrid pipeline capable of operating in out-of-order and in-order modes |
Andrew D. Hilton, Hans M. Jacobson, Brian M. Rogers, Robert A. Shearer, Ken V. Vu +1 more |
2018-10-30 |
$2,799,000 |
| 10095408 |
Reducing negative effects of insufficient data throughput for real-time processing |
Tolga Ozguner, Ishan Jitendra Bhatt, Ryan Scott Haraden, Jeffrey Powers Bradford, Gene Leung |
2018-10-09 |
$102,719,000 |
| 9978118 |
No miss cache structure for real-time image transformations with data compression |
Tolga Ozguner, Gene Leung, Jeffrey Powers Bradford, Adam J. Muff, Ryan Scott Haraden +1 more |
2018-05-22 |
$60,030,000 |
| 9354884 |
Processor with hybrid pipeline capable of operating in out-of-order and in-order modes |
Andrew D. Hilton, Hans M. Jacobson, Brian M. Rogers, Robert A. Shearer, Ken V. Vu +1 more |
2016-05-31 |
$4,553,000 |
| 9092347 |
Allocating cache for use as a dedicated local storage |
Russell D. Hoover, Robert A. Shearer, Alfred T. Watson, III |
2015-07-28 |
$3,451,000 |
| 9053037 |
Allocating cache for use as a dedicated local storage |
Russell D. Hoover, Robert A. Shearer, Alfred T. Watson, III |
2015-06-09 |
$3,292,000 |
| 9021237 |
Low latency variable transfer network communicating variable written to source processing core variable register allocated to destination thread to destination processing core variable register allocated to source thread |
Russell D. Hoover, Robert A. Shearer, Alfred T. Watson, III |
2015-04-28 |
$3,749,000 |
| 8954973 |
Transferring architected state between cores |
Russell D. Hoover, Robert A. Shearer, Alfred T. Watson, III |
2015-02-10 |
$3,717,000 |
| 8949836 |
Transferring architected state between cores |
Russell D. Hoover, Robert A. Shearer, Alfred T. Watson, III |
2015-02-03 |
$3,062,000 |
| 8856602 |
Multi-core processor with internal voting-based built in self test (BIST) |
Jeffrey Douglas Brown, Robert A. Shearer, Alfred T. Watson, III |
2014-10-07 |
$3,450,000 |
| 8719507 |
Near neighbor data cache sharing |
Robert A. Shearer |
2014-05-06 |
$5,370,000 |
| 8719508 |
Near neighbor data cache sharing |
Robert A. Shearer |
2014-05-06 |
$5,370,000 |
| 8560897 |
Hard memory array failure recovery utilizing locking structure |
Mark G. Kupferschmidt, Robert A. Shearer |
2013-10-15 |
$3,582,000 |
