Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10672368 | No miss cache structure for real-time image transformations with multiple LSR processing engines | Ryan Scott Haraden, Tolga Ozguner, Adam J. Muff, Christopher Jon Johnson, Gene Leung +1 more | 2020-06-02 |
| 10572401 | Direct memory access descriptor processing using timestamps | Chad B. McBride, Steven Wheeler, Christopher Jon Johnson, Boris Bobrov, Andras Tantos | 2020-02-25 |
| 10528494 | Direct memory access (“DMA”) descriptor processing using identifiers assigned to descriptors on DMA engines | Chad B. McBride, Steven Wheeler, Christopher Jon Johnson, Boris Bobrov, Andras Tantos | 2020-01-07 |
| 10514753 | Selectively applying reprojection processing to multi-layer scenes for optimizing late stage reprojection power | Ryan Scott Haraden, Miguel Comparan, Adam J. Muff, Gene Leung, Tolga Ozguner | 2019-12-24 |
| 10410349 | Selective application of reprojection processing on layer sub-regions for optimizing late stage reprojection power | Ryan Scott Haraden, Miguel Comparan, Adam J. Muff, Gene Leung, Tolga Ozguner | 2019-09-10 |
| 10403029 | Methods and systems for multistage post-rendering image transformation | Tolga Ozguner, Miguel Comparan, Ryan Scott Haraden | 2019-09-03 |
| 10360832 | Post-rendering image transformation using parallel image transformation pipelines | Tolga Ozguner, Miguel Comparan, Christopher Jon Johnson | 2019-07-23 |
| 10338816 | Reducing negative effects of insufficient data throughput for real-time processing | Tolga Ozguner, Ishan Jitendra Bhatt, Miguel Comparan, Ryan Scott Haraden, Gene Leung | 2019-07-02 |
| 10255891 | No miss cache structure for real-time image transformations with multiple LSR processing engines | Ryan Scott Haraden, Tolga Ozguner, Adam J. Muff, Christopher Jon Johnson, Gene Leung +1 more | 2019-04-09 |
| 10242654 | No miss cache structure for real-time image transformations | Tolga Ozguner, Miguel Comparan, Gene Leung, Adam J. Muff, Ryan Scott Haraden +1 more | 2019-03-26 |
| 10241470 | No miss cache structure for real-time image transformations with data compression | Tolga Ozguner, Gene Leung, Adam J. Muff, Miguel Comparan, Ryan Scott Haraden +1 more | 2019-03-26 |
| 10095408 | Reducing negative effects of insufficient data throughput for real-time processing | Tolga Ozguner, Ishan Jitendra Bhatt, Miguel Comparan, Ryan Scott Haraden, Gene Leung | 2018-10-09 |
| 9978118 | No miss cache structure for real-time image transformations with data compression | Tolga Ozguner, Gene Leung, Adam J. Muff, Miguel Comparan, Ryan Scott Haraden +1 more | 2018-05-22 |
| 9715464 | Direct memory access descriptor processing | Chad B. McBride, Steven Wheeler, Christopher Jon Johnson, Boris Bobrov, Andras Tantos | 2017-07-25 |
| 9047116 | Context switch data prefetching in multithreaded computer | Harold F. Kossman, Timothy John Mullins | 2015-06-02 |
| 8140833 | Implementing polymorphic branch history table reconfiguration | Richard J. Eickemeyer, Timothy H. Heil, Harold F. Kossman, Timothy John Mullins | 2012-03-20 |
| 8141098 | Context switch data prefetching in multithreaded computer | Harold F. Kossman, Timothy John Mullins | 2012-03-20 |
| 8108654 | System and method for a group priority issue schema for a cascaded pipeline | David Arnold Luick | 2012-01-31 |
| 7900024 | Handling data cache misses out-of-order for asynchronous pipelines | Christopher M. Abernathy, Ronald P. Hall, Timothy H. Heil, David Shippy | 2011-03-01 |
| 7739477 | Multiple page size address translation incorporating page size prediction | Jason N. Dale, Kimberly M. Fernsler, Timothy H. Heil, James Allen Rose | 2010-06-15 |
| 7707396 | Data processing system, processor and method of data processing having improved branch target address cache | Richard W. Doing, Richard J. Eickemeyer, Wael R. El-Essawy, Douglas R. G. Logan, Balaram Sinharoy +2 more | 2010-04-27 |
| 7617499 | Context switch instruction prefetching in multithreaded computer | Harold F. Kossman, Timothy John Mullins | 2009-11-10 |
| 7493621 | Context switch data prefetching in multithreaded computer | Harold F. Kossman, Timothy John Mullins | 2009-02-17 |
| 7461239 | Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines | Christopher M. Abernathy, Ronald P. Hall, Timothy H. Heil, David Shippy | 2008-12-02 |
| 7454602 | Pipeline having bifurcated global branch history buffer for indexing branch history table per instruction fetch group | Chris Abernathy, Jason N. Dale, Timothy H. Heil | 2008-11-18 |