CA

Christopher M. Abernathy

IBM: 49 patents #1,780 of 70,183Top 3%
Overall (All Time): #56,270 of 4,157,543Top 2%
49
Patents All Time

Issued Patents All Time

Showing 25 most recent of 49 patents

Patent #TitleCo-InventorsDate
11635961 Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register file Mary D. Brown, Dung Q. Nguyen 2023-04-25
11256507 Thread transition management Mary D. Brown, Susan E. Eisen, James Allan Kahle, Hung Q. Le, Dung Q. Nguyen 2022-02-22
10296339 Thread transition management Mary D. Brown, Susan E. Eisen, James Allan Kahle, Hung Q. Le, Dung Q. Nguyen 2019-05-21
10275251 Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register file Mary D. Brown, Dung Q. Nguyen 2019-04-30
10055226 Thread transition management Mary D. Brown, Susan E. Eisen, James Allan Kahle, Hung Q. Le, Dung Q. Nguyen 2018-08-21
9959121 Bypassing a higher level register file in a processor having a multi-level register file and a set of bypass registers Mary D. Brown, Sundeep Chadha, Dung Q. Nguyen 2018-05-01
9703561 Thread transition management Mary D. Brown, Susan E. Eisen, James Allan Kahle, Hung Q. Le, Dung Q. Nguyen 2017-07-11
9495490 Active power dissipation detection based on erroneus clock gating equations Maarten J. Boersma, Markus Kaltenbach, Ulrike Schmidt 2016-11-15
9286068 Efficient usage of a multi-level register file utilizing a register file bypass Mary D. Brown, Sundeep Chadha, Dung Q. Nguyen 2016-03-15
8874880 Instruction tracking system for processors Hung Q. Le, Dung Q. Nguyen, Benjamin W. Stolt 2014-10-28
8725993 Thread transition management Mary D. Brown, Susan E. Eisen, James Allan Kahle, Hung Q. Le, Dung Q. Nguyen 2014-05-13
8661228 Multi-level register file supporting multiple threads Mary D. Brown, Hung Q. Le, Dung Q. Nguyen 2014-02-25
8661227 Multi-level register file supporting multiple threads Mary D. Brown, Hung Q. Le, Dung Q. Nguyen 2014-02-25
8631223 Register file supporting transactional processing Mary D. Brown, Hung Q. Le, Dung Q. Nguyen 2014-01-14
8521998 Instruction tracking system for processors Hung Q. Le, Dung Q. Nguyen, Benjamin W. Stolt 2013-08-27
8239661 System and method for double-issue instructions using a dependency matrix Mary D. Brown, Todd A. Venton 2012-08-07
8200946 Issue unit for placing a processor into a gradual slow mode of operation Kurt A. Feiste, Ronald P. Hall, Albert J. Van Norstrand, Jr. 2012-06-12
8135942 System and method for double-issue instructions using a dependency matrix and a side issue queue Mary D. Brown, Todd A. Venton, John B. Griswell, Jr. 2012-03-13
8108655 Selecting fixed-point instructions to issue on load-store unit James Wilson Bishop, Mary D. Brown, William E. Burky, Robert A. Cordes, Hung Q. Le +2 more 2012-01-31
8099582 Tracking deallocated load instructions using a dependence matrix Mary D. Brown, William E. Burky, Todd A. Venton 2012-01-17
8082423 Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updates Kurt A. Feiste, David Scott Ray, David Shippy, Albert J. Van Norstrand, Jr. 2011-12-20
8046566 Method to reduce power consumption of a register file with multi SMT support Jens Leenstra, Nicolas Maeding, Dung Q. Nguyen 2011-10-25
8037366 Issuing instructions in-order in an out-of-order processor using false dependencies Mary D. Brown, Dung Q. Nguyen, Todd A. Venton 2011-10-11
8028151 Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines Jonathan James DeMent, Ronald P. Hall, Albert J. Van Norstrand, Jr. 2011-09-27
8020072 Method and apparatus for correcting data errors Todd A. Venton 2011-09-13