Issued Patents All Time
Showing 25 most recent of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11797473 | Accelerator architecture on a programmable platform | Martin Langhammer, Jeffrey R. Eastlack | 2023-10-24 |
| 10095647 | Accelerator architecture on a programmable platform | Martin Langhammer, Jeffrey R. Eastlack | 2018-10-09 |
| 9329666 | Power throttling queue | — | 2016-05-03 |
| 9164570 | Dynamic re-configuration for low power in a data processor | — | 2015-10-20 |
| 8082423 | Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updates | Christopher M. Abernathy, Kurt A. Feiste, David Scott Ray, Albert J. Van Norstrand, Jr. | 2011-12-20 |
| 8051315 | Power throttling apparatus | James Allan Kahle, Albert J. Van Norstrand, Jr. | 2011-11-01 |
| 7953960 | Method and apparatus for delaying a load miss flush until issuing the dependent instruction | Kurt A. Feiste, David Scott Ray, Albert J. Van Norstrand, Jr. | 2011-05-31 |
| 7913070 | Time-of-life counter for handling instruction flushes from a queue | Christopher M. Abernathy, Jonathan James DeMent, Ronald P. Hall, Robert Alan Philhower | 2011-03-22 |
| 7900024 | Handling data cache misses out-of-order for asynchronous pipelines | Christopher M. Abernathy, Jeffrey Powers Bradford, Ronald P. Hall, Timothy H. Heil | 2011-03-01 |
| 7831808 | Queue design system supporting dependency checking and issue for SIMD instructions within a general purpose processor | Christopher M. Abernathy, Jonathan James DeMent, Ronald P. Hall | 2010-11-09 |
| 7769985 | Load address dependency mechanism system and method in a high frequency, low power processor system | Brian D. Barrick, Kimberly M. Fernsler, Dwain A. Hicks, David Scott Ray, Takeki Osanai | 2010-08-03 |
| 7681056 | Dynamic power management in a processor design | Christopher M. Abernathy, Jonathan James DeMent, Ronald P. Hall, Robert Alan Philhower | 2010-03-16 |
| 7596682 | Architected register file system utilizes status and control registers to control read/write operations between threads | — | 2009-09-29 |
| 7496776 | Power throttling method and apparatus | James Allan Kahle, Albert J. Van Norstrand, Jr. | 2009-02-24 |
| 7490224 | Time-of-life counter design for handling instruction flushes from a queue | Christopher M. Abernathy, Jonathan James DeMent, Ronald P. Hall, Robert Alan Philhower | 2009-02-10 |
| 7484052 | Distributed address arbitration scheme for symmetrical multiprocessor system | Brian Mitchell Bass, Thomas L. Jeremiah, Charles Ray Johns, Thuong Quang Truong | 2009-01-27 |
| 7461239 | Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines | Christopher M. Abernathy, Jeffrey Powers Bradford, Ronald P. Hall, Timothy H. Heil | 2008-12-02 |
| 7401242 | Dynamic power management in a processor design | Christopher M. Abernathy, Jonathan James DeMent, Ronald P. Hall, Robert Alan Philhower | 2008-07-15 |
| 7370176 | System and method for high frequency stall design | Jonathan James DeMent, Kurt A. Feiste, Robert Alan Philhower | 2008-05-06 |
| 7363468 | Load address dependency mechanism system and method in a high frequency, low power processor system | Brian D. Barrick, Kimberly Marie Fensler, Dwain A. Hicks, David Scott Ray, Takeki Osanai | 2008-04-22 |
| 7350056 | Method and apparatus for issuing instructions from an issue queue in an information handling system | Christopher M. Abernathy, Jonathan James DeMent, Kurt A. Feiste | 2008-03-25 |
| 7328330 | Queue design supporting dependency checking and issue for SIMD instructions within a general purpose processor | Christopher M. Abernathy, Jonathan James DeMent, Ronald P. Hall | 2008-02-05 |
| 7313673 | Fine grained multi-thread dispatch block mechanism | Christopher M. Abernathy, Jonathan James DeMent, Albert J. Van Norstrand, Jr. | 2007-12-25 |
| 7120748 | Software-controlled cache set management | Michael Norman Day, Harm Peter Hofstee, Charles Johns, James Allan Kahle, Thuong Quang Truong +1 more | 2006-10-10 |
| 7114035 | Software-controlled cache set management with software-generated class identifiers | Michael Norman Day, Harm Peter Hofstee, Charles Ray Johns, James Allan Kahle, Thuong Quang Truong +1 more | 2006-09-26 |