Issued Patents All Time
Showing 26–50 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7103748 | Memory management for real-time applications | Michael Norman Day, Harm Peter Hofstee, Charles Ray Johns, James Allan Kahle, Thuong Quang Truong | 2006-09-05 |
| 7093080 | Method and apparatus for coherent memory structure of heterogeneous processor systems | Michael Norman Day, Harm Peter Hofstee, Charles Ray Johns, James Allan Kahle, Thuong Quang Truong | 2006-08-15 |
| 7062612 | Updating remote locked cache | Jeffrey Douglas Brown, Michael Norman Day, Charles Ray Johns, James Allan Kahle, Thuong Quang Truong | 2006-06-13 |
| 6981072 | Memory management in multiprocessor system | Michael Norman Day, Harm Peter Hofstee, Charles Ray Johns, James Allan Kahle, Thuong Quang Truong | 2005-12-27 |
| 6961820 | System and method for identifying and accessing streaming data in a locked portion of a cache | Michael Norman Day, Charles Ray Johns, James Allan Kahle, Peichun Peter Liu, Thuong Quang Truong | 2005-11-01 |
| 6957305 | Data streaming mechanism in a microprocessor | David Scott Ray | 2005-10-18 |
| 6820143 | On-chip data transfer in multi-processor system | Michael Norman Day, Charles Ray Johns, James Allan Kahle, Peichun Peter Liu, Thuong Quang Truong | 2004-11-16 |
| 6658555 | Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipeline | James Allan Kahle, Hung Q. Le, Charles Roberts Moore, Larry Edward Thatcher | 2003-12-02 |
| 6654876 | System for rejecting and reissuing instructions after a variable delay time period | Hung Q. Le | 2003-11-25 |
| 6543002 | Recovery from hang condition in a microprocessor | James Allan Kahle, Hung Q. Le, Kevin F. Reick, Larry Edward Thatcher | 2003-04-01 |
| 6490653 | Method and system for optimally issuing dependent instructions based on speculative L2 cache hit in a data processing system | Robert Alan Cargnoni, Bruce Joseph Ronchetti, Larry Edward Thatcher | 2002-12-03 |
| 6349382 | System for store forwarding assigning load and store instructions to groups and reorder queues to keep track of program order | Kurt A. Feiste, Bruce Joseph Ronchetti | 2002-02-19 |
| 6336168 | System and method for merging multiple outstanding load miss instructions | Marlin Wayne Frederick, Jr., Bruce Joseph Ronchetti, Larry Edward Thatcher | 2002-01-01 |
| 6336183 | System and method for executing store instructions | Hung Q. Le, Robert G. McDonald, Larry Edward Thatcher | 2002-01-01 |
| 6298436 | Method and system for performing atomic memory accesses in a processor system | James Allan Kahle, Hung Q. Le, Larry Edward Thatcher | 2001-10-02 |
| 6289428 | Superscaler processor and method for efficiently recovering from misaligned data addresses | John Edward Derrick, Hung Q. Le, Larry Edward Thatcher | 2001-09-11 |
| 6237081 | Queuing method and apparatus for facilitating the rejection of sequential instructions in a processor | Hung Q. Le, Larry Edward Thatcher, Bruce Joseph Ronchetti | 2001-05-22 |
| 6226722 | Integrated level two cache and controller with multiple ports, L1 bypass and concurrent accessing | David B. Shuler | 2001-05-01 |
| 6061780 | Execution unit chaining for single cycle extract instruction having one serial shift left and one serial shift right execution units | Jerald G. Leach | 2000-05-09 |
| 6003125 | High performance adder for multiple parallel add operations | — | 1999-12-14 |
| 5822755 | Dual usage memory selectively behaving as a victim cache for L1 cache or as a tag array for L2 cache | — | 1998-10-13 |
| 5822758 | Method and system for high performance dynamic and user programmable cache arbitration | Albert J. Loper, Timothy A. Elliott, Christopher H. Olson | 1998-10-13 |
| 5210828 | Multiprocessing system with interprocessor communications facility | Timothy V. Bolan, Josephine A. Boston, George A. Fax, Donald J. Hanrahan, Bernhard Laubli +2 more | 1993-05-11 |
| 4974147 | Programmable quiesce apparatus for retry, recovery and debug | Donald J. Hanrahan, Bruce Morehead | 1990-11-27 |
| 4961140 | Apparatus and method for extending a parallel synchronous data and message bus | Gerald George Pechanek, Mark C. Snedaker, Sandra S. Woodward | 1990-10-02 |