Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7577794 | Low latency coherency protocol for a multi-chip multiprocessor system | Bruce Beukema, Russell D. Hoover, Jon K. Kriegel, Eric O. Mejdrich | 2009-08-18 |
| 7475190 | Direct access of cache lock set data without backing memory | Russell D. Hoover, Eric O. Mejdrich | 2009-01-06 |
| 7355601 | System and method for transfer of data between processors using a locked set, head and tail pointers | Jeffrey Andrews, Nicholas R. Baker, J. Andrew Goossen, Russell D. Hoover, Eric O. Mejdrich | 2008-04-08 |
| 7305524 | Snoop filter directory mechanism in coherency shared memory system | Russell D. Hoover, Eric O. Mejdrich, Jon K. Kriegel | 2007-12-04 |
| 6791352 | Method and apparatus for debugging a chip | David Joel Verdoorn | 2004-09-14 |
| 6134699 | Method and apparatus for detecting virtual address parity error for a translation lookaside buffer | James A. Steenburgh | 2000-10-17 |
| 6044447 | Method and apparatus for communicating translation command information in a multithreaded environment | Duane A. Averill, John Michael Borkenhagen, James A. Steenburgh | 2000-03-28 |
| 4961140 | Apparatus and method for extending a parallel synchronous data and message bus | Gerald George Pechanek, David Shippy, Mark C. Snedaker | 1990-10-02 |
| 4943984 | Data processing system parallel data bus having a single oscillator clocking apparatus | Gerald George Pechanek, David Shippy, Mark C. Snedaker | 1990-07-24 |