Issued Patents All Time
Showing 25 most recent of 83 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11531550 | Program thread selection between a plurality of execution pipelines | Robert T. Golla | 2022-12-20 |
| 10423389 | Methods for constructing lookup tables for division and square-root implementations | Josephus C. Ebergen, Dmitry Nadezhin | 2019-09-24 |
| 10353670 | Floating point unit with support for variable length numbers | Jeffrey S. Brooks, Hesam Fathi Moghadam, Josephus C. Ebergen | 2019-07-16 |
| 10289386 | Iterative division with reduced latency | Josephus C. Ebergen, Dmitry Nadehzin, David Lawrence Rager, Austin Lee | 2019-05-14 |
| 10198260 | Processing instruction control transfer instructions | Manish K. Shah | 2019-02-05 |
| 10180819 | Processing fixed and variable length numbers | Jeffrey S. Brooks, Eugene Karichkin | 2019-01-15 |
| 9747073 | Floating point unit with support for variable length numbers | Jeffrey S. Brooks, Hesam Fathi Moghadam, Josephus C. Ebergen | 2017-08-29 |
| 9569258 | Scheduling multiple operations in a divider unit | Jeffrey S. Brooks | 2017-02-14 |
| 9507656 | Mechanism for handling unfused multiply-accumulate accrued exception bits in a processor | Jeffrey S. Brooks, Paul J. Jordan | 2016-11-29 |
| 9507564 | Processing fixed and variable length numbers | Jeffrey S. Brooks, Eugene Karichkin | 2016-11-29 |
| 9317286 | Apparatus and method for implementing instruction support for the camellia cipher algorithm | Gregory F. Grohoski, Lawrence Spracklen | 2016-04-19 |
| 9304767 | Single cycle data movement between general purpose and floating-point registers | Robert T. Golla, Jeffrey S. Brooks | 2016-04-05 |
| 9086890 | Division unit with normalization circuit and plural divide engines for receiving instructions when divide engine availability is indicated | Jeffrey S. Brooks, Matthew B. Smittle | 2015-07-21 |
| 8977670 | Processor pipeline which implements fused and unfused multiply-add instructions | Jeffrey S. Brooks | 2015-03-10 |
| 8892622 | Pipelined divide circuit for small operand sizes | Jeffrey S. Brooks | 2014-11-18 |
| 8886920 | Associating tag to branch instruction to access array storing predicted target addresses for page crossing targets for comparison with resolved address at execution stage | Manish K. Shah | 2014-11-11 |
| 8862861 | Suppressing branch prediction information update by branch instructions in incorrect speculative execution path | Manish K. Shah | 2014-10-14 |
| 8832464 | Processor and method for implementing instruction support for hash algorithms | Jeffrey S. Brooks, Robert T. Golla | 2014-09-09 |
| 8671129 | System and method of bypassing unrounded results in a multiply-add pipeline unit | Jeffrey S. Brooks | 2014-03-11 |
| 8654970 | Apparatus and method for implementing instruction support for the data encryption standard (DES) algorithm | Gregory F. Grohoski, Lawrence Spracklen | 2014-02-18 |
| 8583902 | Instruction support for performing montgomery multiplication | Gregory F. Grohoski, Lawrence Spracklen, Nils Gura | 2013-11-12 |
| 8560814 | Thread fairness on a multi-threaded processor with multi-cycle cryptographic operations | Robert T. Golla, Gregory F. Grohoski | 2013-10-15 |
| 8555038 | Processor and method providing instruction support for instructions that utilize multiple register windows | Paul J. Jordan, Jama I. Barreh | 2013-10-08 |
| 8468425 | Register error correction of speculative data in an out-of-order processor | Paul J. Jordan | 2013-06-18 |
| 8458446 | Accessing a multibank register file using a thread identifier | Xiang Li, Robert T. Golla | 2013-06-04 |