Issued Patents All Time
Showing 25 most recent of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12340195 | Handling interrupts from a virtual function in a system with a reconfigurable processor | Manish K. Shah, Maran WILSON, Ravinder Kumar | 2025-06-24 |
| 12277041 | Method for migrating CPU state from an inoperable core to a spare core | James M. Lewis, Gregory Onufer, Ali Vahidsafa | 2025-04-15 |
| 12271333 | Peer-to-peer route through in a reconfigurable computing system | Manish K. Shah, Emre Ali Burhan, Dawei Huang, Yong Qin | 2025-04-08 |
| 12243604 | Scannable memory array and a method for scanning memory | Thomas A. Ziaja | 2025-03-04 |
| 12147339 | Non-uniform memory interleaving processor | Manish K. Shah | 2024-11-19 |
| 12079124 | Non-uniform memory interleave method | Manish K. Shah | 2024-09-03 |
| 11709742 | Method for migrating CPU state from an inoperable core to a spare core | James M. Lewis, Gregory Onufer, Ali Vahidsafa | 2023-07-25 |
| 11263012 | Method for migrating CPU state from an inoperable core to a spare core | James M. Lewis, Gregory Onufer, Ali Vahidsafa | 2022-03-01 |
| 10740102 | Hardware mechanism to mitigate stalling of a processor core | Munsefar Khaleque, Nathan Francis Sheeley, Mark Greenberg, Matthew B. Smittle | 2020-08-11 |
| 10528351 | Method for migrating CPU state from an inoperable core to a spare core | James M. Lewis, Gregory Onufer, Ali Vahidsafa | 2020-01-07 |
| 9971565 | Storage, access, and management of random numbers generated by a central random number generator and dispensed to hardware threads of cores | John D. Pape, Mark Luttrell, Michael Snyder | 2018-05-15 |
| 9940132 | Load-monitor mwait | Paul N. Loewenstein, Mark Luttrell | 2018-04-10 |
| 9710273 | Method for migrating CPU state from an inoperable core to a spare core | James M. Lewis, Gregory Onufer, Ali Vahidsafa | 2017-07-18 |
| 9672298 | Precise excecution of versioned store instructions | Zoran Radovic, Jared C. Smolens, Robert T. Golla, Mark Luttrell | 2017-06-06 |
| 9507656 | Mechanism for handling unfused multiply-accumulate accrued exception bits in a processor | Jeffrey S. Brooks, Christopher H. Olson | 2016-11-29 |
| 8732430 | Method and apparatus for using unused bits in a memory pointer | Zoran Radovic, Graham Ricketson Murphy, John G. Johnson | 2014-05-20 |
| 8555038 | Processor and method providing instruction support for instructions that utilize multiple register windows | Christopher H. Olson, Jama I. Barreh | 2013-10-08 |
| 8504805 | Processor operating mode for mitigating dependency conditions between instructions having different operand sizes | Robert T. Golla, Jama I. Barreh, Matthew B. Smittle, Yuan C. Chou, Jared C. Smolens | 2013-08-06 |
| 8468425 | Register error correction of speculative data in an out-of-order processor | Christopher H. Olson | 2013-06-18 |
| 8438208 | Processor and method for implementing instruction support for multiplication of large operands | Christopher H. Olson, Jeffrey S. Brooks, Robert T. Golla | 2013-05-07 |
| 8429386 | Dynamic tag allocation in a multithreaded out-of-order processor | Robert T. Golla, Jama I. Barreh | 2013-04-23 |
| 8412911 | System and method to invalidate obsolete address translations | Gregory F. Grohoski, Mark Luttrell, Zeid H. Samoail | 2013-04-02 |
| 8301865 | System and method to manage address translation requests | Gregory F. Grohoski, Mark Luttrell, Zeid H. Samoail, Robert T. Golla | 2012-10-30 |
| 8190864 | APIC implementation for a highly-threaded x86 processor | Gregory F. Grohoski | 2012-05-29 |
| 8099586 | Branch misprediction recovery mechanism for microprocessors | Yuan C. Chou, Robert T. Golla, Mark Luttrell, Manish K. Shah | 2012-01-17 |