Issued Patents All Time
Showing 25 most recent of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12321751 | Re-use of speculative control transfer instruction results from wrong path | Deepankar Duggal, Debasish Chandra, Niket K. Choudhary, Richard F. Russo | 2025-06-03 |
| 12175248 | Re-use of speculative load instruction results from wrong path | Deepankar Duggal, Debasish Chandra, Niket K. Choudhary, Richard F. Russo | 2024-12-24 |
| 12159142 | Managing table accesses for tagged geometric length (TAGE) load value prediction | Chang Xu, Deepankar Duggal, Debasish Chandra | 2024-12-03 |
| 12067398 | Shared learning table for load value prediction and load address prediction | Debasish Chandra, Mridul Agarwal, Haoyan Jia | 2024-08-20 |
| 12045615 | Processing of synchronization barrier instructions | Deepankar Duggal, Kulin N. Kothari, Mridul Agarwal, Chang Xu, Yanran Yang +2 more | 2024-07-23 |
| 11829763 | Early load execution via constant address and stride prediction | Viney Gautam, Wei-Han Lien, Kulin N. Kothari, Mridul Agarwal | 2023-11-28 |
| 11126555 | Multi-line data prefetching using dynamic prefetch depth | Hyunjin Lee, John D. Pape | 2021-09-21 |
| 11099849 | Method for reducing fetch cycles for return-type instructions | Manish K. Shah, Richa Aggarwal | 2021-08-24 |
| 10747540 | Hybrid lookahead branch target cache | Manish K. Shah | 2020-08-18 |
| 10579531 | Multi-line data prefetching using dynamic prefetch depth | Hyunjin Lee, John D. Pape | 2020-03-03 |
| 10474578 | Utilization-based throttling of hardware prefetchers | Hyunjin Lee, John D. Pape | 2019-11-12 |
| 10430342 | Optimizing thread selection at fetch, select, and commit stages of processor core pipeline | Gideon N. Levinsky, Manish K. Shah, Robert T. Golla, Matthew B. Smittle | 2019-10-01 |
| 10296460 | Prefetch bandwidth throttling by dynamically adjusting miss buffer prefetch-dropping thresholds | Suraj Sudhir | 2019-05-21 |
| 10073789 | Method for load instruction speculation past older store instructions | — | 2018-09-11 |
| 10013356 | Facilitating prefetching for data streams with multiple strides | — | 2018-07-03 |
| 9946543 | Processor efficiency by combining working and architectural register files | — | 2018-04-17 |
| 9785574 | Translation lookaside buffer that employs spacial locality | — | 2017-10-10 |
| 9690707 | Correlation-based instruction prefetching | — | 2017-06-27 |
| 9665375 | Mitigation of thread hogs on a threaded processor and prevention of allocation of resources to one or more instructions following a load miss | Robert T. Golla, Mark Luttrell | 2017-05-30 |
| 9535697 | Register window performance via lazy register fills | — | 2017-01-03 |
| 9442727 | Filtering out redundant software prefetch instructions | — | 2016-09-13 |
| 9367312 | Processor efficiency by combining working and architectural register files | — | 2016-06-14 |
| 9304927 | Adaptive stride prefetcher | Suryanarayana Murthy Durbhakula | 2016-04-05 |
| 9256541 | Dynamically adjusting the hardware stream prefetcher prefetch ahead distance | Vijay Sathish | 2016-02-09 |
| 9110811 | Prefetching method and apparatus | — | 2015-08-18 |