Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12321746 | DSB operation with excluded region | Jeff Gonion, John H. Kelm, James Vash, Pradeep Kanapathipillai, Mridul Agarwal +2 more | 2025-06-03 |
| 12314200 | Scalable interrupts | Jeffrey E. Gonion, Charles E. Tucker, Tal Kuzi, Richard F. Russo, Mridul Agarwal +3 more | 2025-05-27 |
| 12298915 | Hierarchical store queue circuit | Nikhil Gupta, Kulin N. Kothari, Mridul Agarwal, Pankaj Lnu | 2025-05-13 |
| 12229557 | Atomic operation predictor to predict whether an atomic operation will complete successfully | Brian R. Mestan, Michael L. Karm | 2025-02-18 |
| 12007920 | Scalable interrupts | Jeffrey E. Gonion, Charles E. Tucker, Tal Kuzi, Richard F. Russo, Mridul Agarwal +3 more | 2024-06-11 |
| 11928467 | Atomic operation predictor to predict whether an atomic operation will complete successfully | Brian R. Mestan, Michael L. Karm | 2024-03-12 |
| 11914511 | Decoupling atomicity from operation size | Francesco Spadini, Mridul Agarwal | 2024-02-27 |
| 11720360 | DSB operation with excluded region | Jeff Gonion, John H. Kelm, James Vash, Pradeep Kanapathipillai, Mridul Agarwal +2 more | 2023-08-08 |
| 11630789 | Scalable interrupts | Jeffrey E. Gonion, Charles E. Tucker, Tal Kuzi, Richard F. Russo, Mridul Agarwal +3 more | 2023-04-18 |
| 11347514 | Content-addressable memory filtering based on microarchitectural state | Deepak Limaye, Brian R. Mestan | 2022-05-31 |
| 11256622 | Dynamic adaptive drain for write combining buffer | Michael L. Karm | 2022-02-22 |
| 11119767 | Atomic operation predictor to predict if an atomic operation will successfully complete and a store queue to selectively forward data based on the predictor | Brian R. Mestan, Michael L. Karm | 2021-09-14 |
| 11099990 | Managing serial miss requests for load operations in a non-coherent memory system | Brian R. Mestan, Deepak Limaye, Mridul Agarwal | 2021-08-24 |
| 10831675 | Adaptive tablewalk translation storage buffer predictor | John D. Pape, Manish K. Shah, Jared C. Smolens | 2020-11-10 |
| 10430342 | Optimizing thread selection at fetch, select, and commit stages of processor core pipeline | Yuan C. Chou, Manish K. Shah, Robert T. Golla, Matthew B. Smittle | 2019-10-01 |
| 10331567 | Prefetch circuit with global quality factor to reduce aggressiveness in low power modes | Stephan G. Meier, Tyler J. Huberty, Nikhil Gupta, Francesco Spadini | 2019-06-25 |
| 10255197 | Adaptive tablewalk translation storage buffer predictor | John D. Pape, Manish K. Shah, Jared C. Smolens | 2019-04-09 |
| 9208261 | Power reduction for fully associated translation lookaside buffer (TLB) and content addressable memory (CAM) | Manish K. Shah | 2015-12-08 |
| 9146744 | Store queue having restricted and unrestricted entries | Paul Caprioli, Martin Karlsson, Shailender Chaudhry | 2015-09-29 |
| 8732438 | Anti-prefetch instruction | Paul Caprioli, Sherman H. Yip | 2014-05-20 |
| 8601240 | Selectively defering load instructions after encountering a store instruction with an unknown destination address during speculative execution | Shailender Chaudhry, Martin Karlsson | 2013-12-03 |
| 8595464 | Dynamic sizing of translation lookaside buffer for power reduction | Manish K. Shah | 2013-11-26 |
| 8065485 | Method and apparatus for determining cache storage locations based on latency requirements | Paul Caprioli, Sherman H. Yip | 2011-11-22 |
| 7934080 | Aggressive store merging in a processor that supports checkpointing | Paul Caprioli, Martin Karlsson, Khondakar A. Mujtaba, Shailender Chaudhry, Murali K. Inaganti | 2011-04-26 |
| 7293221 | Methods and systems for detecting memory address transfer errors in an address bus | Samson Wong, Kandasamy Aravinthan, Shahar Dor, Richard Van, Jiejun Lu | 2007-11-06 |