Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10430050 | Apparatus and associated methods for editing images | Dan Spjuth, Shahil Soni, David Fredh, Esa Kankaanpää, Johan Windmark +1 more | 2019-10-01 |
| 10346011 | User interface for the application of image effects to images | Dan Spjuth, Shahil Soni, David Fredh, Esa Kankaanpää, Johan Windmark +1 more | 2019-07-09 |
| 9146744 | Store queue having restricted and unrestricted entries | Paul Caprioli, Shailender Chaudhry, Gideon N. Levinsky | 2015-09-29 |
| 9086889 | Reducing pipeline restart penalty | Sherman H. Yip, Shailender Chaudhry | 2015-07-21 |
| 8984264 | Precise data return handling in speculative processors | Sherman H. Yip, Shailender Chaudhry | 2015-03-17 |
| 8688963 | Checkpoint allocation in a speculative processor | Shailender Chaudhry, Sherman H. Yip | 2014-04-01 |
| 8635428 | Preventing duplicate entries in a non-blocking TLB structure that supports multiple page sizes | Jing-Ming Chang | 2014-01-21 |
| 8601240 | Selectively defering load instructions after encountering a store instruction with an unknown destination address during speculative execution | Shailender Chaudhry, Gideon N. Levinsky | 2013-12-03 |
| 8484434 | Index generation for cache memories | Paul Caprioli, Shailender Chaudhry | 2013-07-09 |
| 8418099 | Performance counters for integrated circuits | — | 2013-04-09 |
| 8341357 | Pre-fetching for a sibling cache | Shailender Chaudhry, Robert E. Cypher | 2012-12-25 |
| 8327188 | Hardware transactional memory acceleration through multiple failure recovery | Sherman H. Yip, Shailender Chaudhry | 2012-12-04 |
| 8285926 | Cache access filtering for processors without secondary miss detection | — | 2012-10-09 |
| 8281185 | Advice-based feedback for transactional execution | Daniel S. Nussbaum, David Dice, Mark S. Moir | 2012-10-02 |
| 8225139 | Facilitating transactional execution through feedback about misspeculation | Daniel S. Nussbaum, David Dice, Mark S. Moir | 2012-07-17 |
| 8151084 | Using address and non-address information for improved index generation for cache memories | Paul Caprioli, Shailender Chaudhry | 2012-04-03 |
| 8041900 | Method and apparatus for improving transactional memory commit latency | Paul Caprioli, Sherman H. Yip | 2011-10-18 |
| 7979640 | Cache line duplication in response to a way prediction conflict | Shailender Chaudhry, Robert E. Cypher | 2011-07-12 |
| 7934080 | Aggressive store merging in a processor that supports checkpointing | Paul Caprioli, Gideon N. Levinsky, Khondakar A. Mujtaba, Shailender Chaudhry, Murali K. Inaganti | 2011-04-26 |
| 7774531 | Allocating processor resources during speculative execution using a temporal ordering policy | — | 2010-08-10 |