Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10140312 | Low latency distributed storage service | Jacob A. Strauss, Mark Allen Fogleman, Edward William Naim, Jacob David Luszcz, Michael Robert Frasca +5 more | 2018-11-27 |
| 9374588 | Rate control method and system | Matteo Frigo | 2016-06-21 |
| 8560816 | System and method for performing incremental register checkpointing in transactional memory | Mark S. Moir, David Dice, James R. Goodman | 2013-10-15 |
| 8539491 | Thread scheduling in chip multithreading processors | Christopher A. Small, Alexandra Fedorova | 2013-09-17 |
| 8490101 | Thread scheduling in chip multithreading processors | Christopher A. Small, Alexandra Fedorova | 2013-07-16 |
| 8464261 | System and method for executing a transaction using parallel co-transactions | Mark S. Moir, Robert E. Cypher | 2013-06-11 |
| 8402227 | System and method for committing results of a software transaction using a hardware transaction | Mark S. Moir, Yosef Lev | 2013-03-19 |
| 8281185 | Advice-based feedback for transactional execution | David Dice, Martin Karlsson, Mark S. Moir | 2012-10-02 |
| 8239635 | System and method for performing visible and semi-visible read operations in a software transactional memory | Yosef Lev, Mark S. Moir | 2012-08-07 |
| 8225139 | Facilitating transactional execution through feedback about misspeculation | David Dice, Martin Karlsson, Mark S. Moir | 2012-07-17 |
| 8214833 | Systems and methods for supporting software transactional memory using inconsistency-aware compilers and libraries | Mark S. Moir | 2012-07-03 |
| 7966459 | System and method for supporting phased transactional memory modes | Mark S. Moir | 2011-06-21 |
| 7945912 | Hierarchical queue-based locks | Nir N. Shavit, Victor M. Luchangco | 2011-05-17 |
| 7779165 | Scalable method for producer and consumer elimination | Mark S. Moir, Ori Shalev, Nir N. Shavit | 2010-08-17 |
| 7496726 | Controlling contention via transactional timers among conflicting transactions issued by processors operating in insistent or polite mode | Victor M. Luchangco, Mark S. Moir, Ori Shalev, Nir N. Shavit | 2009-02-24 |
| 7353342 | Shared lease instruction support for transient blocking synchronization | Mark S. Moir, Nir N. Shavit, Guy L. Steele, Jr. | 2008-04-01 |
| 7346747 | Exclusive lease instruction support for transient blocking synchronization | Mark S. Moir, Nir N. Shavit, Guy L. Steele, Jr. | 2008-03-18 |