Issued Patents All Time
Showing 25 most recent of 133 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11809319 | Contention tracking for processor cache management | Anurag Chaudhary, Christopher Richard Feilbach, Jasjit Singh, Manuel Gautho, Aprajith Thirumalai | 2023-11-07 |
| 11789869 | Contention tracking for latency reduction of exclusive operations | Anurag Chaudhary, Christopher Richard Feilbach, Jasjit Singh, Manuel Gautho, Aprajith Thirumalai | 2023-10-17 |
| 10642744 | Memory type which is cacheable yet inaccessible by speculative instructions | Darrell D. Boggs, Ross Segelken, Mike Cornaby, Nick Fortino, Denis M. Khartikov +3 more | 2020-05-05 |
| 9471395 | Processor cluster migration techniques | Sagheer Ahmad, John George Mathieson, Mark A. Overby | 2016-10-18 |
| 9280343 | Store queue with token to facilitate efficient thread synchronization | Haakan E. Zeffer, Robert E. Cypher | 2016-03-08 |
| 9268710 | Facilitating efficient transactional memory and atomic operations via cache line marking | Robert E. Cypher | 2016-02-23 |
| 9256438 | Mechanism for increasing the effective capacity of the working register file | Paul Caprioli, Marc Tremblay | 2016-02-09 |
| 9146744 | Store queue having restricted and unrestricted entries | Paul Caprioli, Martin Karlsson, Gideon N. Levinsky | 2015-09-29 |
| 9086889 | Reducing pipeline restart penalty | Martin Karlsson, Sherman H. Yip | 2015-07-21 |
| 8984264 | Precise data return handling in speculative processors | Martin Karlsson, Sherman H. Yip | 2015-03-17 |
| 8898436 | Method and structure for solving the evil-twin problem | Marc Tremblay | 2014-11-25 |
| 8745419 | Logical power throttling of instruction decode rate for successive time periods | Quinn A. Jacobson, Marc Tremblay | 2014-06-03 |
| 8732407 | Deadlock avoidance during store-mark acquisition | Robert E. Cypher, Haakan E. Zeffer | 2014-05-20 |
| 8688963 | Checkpoint allocation in a speculative processor | Martin Karlsson, Sherman H. Yip | 2014-04-01 |
| 8627044 | Issuing instructions with unresolved data dependencies | Richard Van, Robert E. Cypher, Debasish Chandra | 2014-01-07 |
| 8601240 | Selectively defering load instructions after encountering a store instruction with an unknown destination address during speculative execution | Martin Karlsson, Gideon N. Levinsky | 2013-12-03 |
| 8484434 | Index generation for cache memories | Paul Caprioli, Martin Karlsson | 2013-07-09 |
| 8447931 | Processor with a register file that supports multiple-issue execution | Paul Caprioli, Marc Tremblay | 2013-05-21 |
| 8364900 | Pseudo-LRU cache line replacement for a high-speed cache | Paul Caprioli, Sherman H. Yip | 2013-01-29 |
| 8341357 | Pre-fetching for a sibling cache | Martin Karlsson, Robert E. Cypher | 2012-12-25 |
| 8327188 | Hardware transactional memory acceleration through multiple failure recovery | Martin Karlsson, Sherman H. Yip | 2012-12-04 |
| 8219831 | Reducing temperature and power by instruction throttling at decode stage of processor pipeline in time constant duration steps | Quinn A. Jacobson, Marc Tremblay | 2012-07-10 |
| 8151084 | Using address and non-address information for improved index generation for cache memories | Paul Caprioli, Martin Karlsson | 2012-04-03 |
| 8006073 | Simultaneous speculative threading light mode | Abid Ali | 2011-08-23 |
| 7979640 | Cache line duplication in response to a way prediction conflict | Robert E. Cypher, Martin Karlsson | 2011-07-12 |