| 9086889 |
Reducing pipeline restart penalty |
Martin Karlsson, Shailender Chaudhry |
2015-07-21 |
| 8984264 |
Precise data return handling in speculative processors |
Martin Karlsson, Shailender Chaudhry |
2015-03-17 |
| 8732438 |
Anti-prefetch instruction |
Paul Caprioli, Gideon N. Levinsky |
2014-05-20 |
| 8688963 |
Checkpoint allocation in a speculative processor |
Shailender Chaudhry, Martin Karlsson |
2014-04-01 |
| 8572356 |
Space-efficient mechanism to support additional scouting in a processor using checkpoints |
Paul Caprioli |
2013-10-29 |
| 8364900 |
Pseudo-LRU cache line replacement for a high-speed cache |
Paul Caprioli, Shailender Chaudhry |
2013-01-29 |
| 8327188 |
Hardware transactional memory acceleration through multiple failure recovery |
Martin Karlsson, Shailender Chaudhry |
2012-12-04 |
| 8316366 |
Facilitating transactional execution in a processor that supports simultaneous speculative threading |
Paul Caprioli, Marc Tremblay |
2012-11-20 |
| 8181002 |
Merging checkpoints in an execute-ahead processor |
Paul Caprioli, Marc Tremblay |
2012-05-15 |
| 8065485 |
Method and apparatus for determining cache storage locations based on latency requirements |
Gideon N. Levinsky, Paul Caprioli |
2011-11-22 |
| 8041900 |
Method and apparatus for improving transactional memory commit latency |
Paul Caprioli, Martin Karlsson |
2011-10-18 |
| 7757068 |
Method and apparatus for measuring performance during speculative execution |
Paul Caprioli, Shailender Chaudhry |
2010-07-13 |
| 7716457 |
Method and apparatus for counting instructions during speculative execution |
Paul Caprioli, Shailender Chaudhry |
2010-05-11 |
| 7650487 |
Method and structure for coordinating instruction execution in out-of-order processor execution using an instruction including an artificial register dependency |
Shailender Chaudhry, Paul Caprioli |
2010-01-19 |
| 7634639 |
Avoiding live-lock in a processor that supports speculative execution |
Shailender Chaudhry, Paul Caprioli, Guarav Garg, Ketaki Rao |
2009-12-15 |
| 7617421 |
Method and apparatus for reporting failure conditions during transactional execution |
Paul Caprioli, Shailender Chaudhry |
2009-11-10 |
| 7610474 |
Mechanism for hardware tracking of return address after tail call elimination of return-type instruction |
Paul Caprioli, Shailender Chaudhry |
2009-10-27 |
| 7480787 |
Method and structure for pipelining of SIMD conditional moves |
Paul Caprioli, Lawrence Spracklen |
2009-01-20 |
| 7461208 |
Circuitry and method for accessing an associative cache with parallel determination of data and data availability |
Paul Caprioli, Shailender Chaudhry |
2008-12-02 |
| 7418581 |
Method and apparatus for sampling instructions on a processor that supports speculative execution |
Shailender Chaudhry, Paul Caprioli |
2008-08-26 |
| 7331039 |
Method for graphically displaying hardware performance simulators |
Paul Caprioli |
2008-02-12 |
| 7293163 |
Method and apparatus for dynamically adjusting the aggressiveness of an execute-ahead processor to hide memory latency |
Paul Caprioli |
2007-11-06 |
| 7257700 |
Avoiding register RAW hazards when returning from speculative execution |
Shailender Chaudhry, Paul Caprioli, Marc Tremblay |
2007-08-14 |
