Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for dynamically adjusting the aggressiveness of an execute-ahead processor to hide memory latency

Method and apparatus for dynamically adjusting the aggressiveness of an execute-ahead processor to hide memory latency

US Patent 7293163 · Granted Nov 6, 2007

Estimated economic value: $4,193,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Systems, methods, and apparatuses for heterogeneous computing2024
Systems, methods, and apparatuses for heterogeneous computing2023
Systems, methods, and apparatuses for heterogeneous computing2022
Systems, methods, and apparatuses for heterogeneous computing2021
Systems, methods, and apparatuses for last branch record support compatible with2021
Technologies for translation cache management in binary translation systems2021
Apparatuses, methods, and systems for swizzle operations in a configurable spati2020
Instruction and logic to perform dynamic binary translation2020
Control-flow integrity with managed code and unmanaged code2020
State recovery methods and apparatus for computing platforms2020
Package acceptance, guidance, and refuel system for drone technology2019
Apparatus and method for architectural performance monitoring in binary translat2019