Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12360836 | Datalogging circuit triggered by a watchdog timer | Richard H. Larson, Charles J. Fleckenstein | 2025-07-15 |
| 12332834 | Universal serial bus time synchronization | Alexei E. Kosut, Yi-Chun Chen | 2025-06-17 |
| 12321746 | DSB operation with excluded region | Jeff Gonion, James Vash, Pradeep Kanapathipillai, Mridul Agarwal, Gideon N. Levinsky +2 more | 2025-06-03 |
| 11914521 | Cache quota control | Wolfgang H. Klingauf, Muhammad Umer Amjad, Connie W. Cheung, Yueh-Ta Wu, Muditha Kanchana | 2024-02-27 |
| 11853148 | Datalogging circuit triggered by a watchdog timer | Richard H. Larson, Charles J. Fleckenstein | 2023-12-26 |
| 11842700 | Backlight reconstruction and compensation-based throttling | Prabhu Rajamani, Liang Deng, Oren Kerem, Meir Harar, Ido Yaacov Soffair +2 more | 2023-12-12 |
| 11720360 | DSB operation with excluded region | Jeff Gonion, James Vash, Pradeep Kanapathipillai, Mridul Agarwal, Gideon N. Levinsky +2 more | 2023-08-08 |
| 11720520 | Universal serial bus time synchronization | Alexei E. Kosut, Yi-Chun Chen | 2023-08-08 |
| 11594189 | Backlight reconstruction and compensation-based throttling | Prabhu Rajamani, Liang Deng, Oren Kerem, Meir Harar, Ido Yaacov Soffair +2 more | 2023-02-28 |
| 11550745 | Remapping techniques for message signaled interrupts | — | 2023-01-10 |
| 11501820 | Selective reference voltage calibration in memory subsystem | Robert E. Jeter, Kai Lun Hsiung, Rakesh L. Notani, Venkata Ramana Malladi, Taehyun Kim | 2022-11-15 |
| 11226752 | Filtering memory calibration | Rakesh L. Notani, Robert E. Jeter, Suhas Kumar Suvarna Ramesh, Naveen Kumar Korada, Mohammad Rizwan +2 more | 2022-01-18 |
| 11169585 | Dashboard with push model for receiving sensor data | Achmed R. Zahir, Inder M. Sodhi | 2021-11-09 |
| 10496572 | Intracluster and intercluster interprocessor interrupts including a retract interrupt that causes a previous interrupt to be canceled | Bernard J. Semeria, Joshua P. de Cesare, Shih-Chieh Wen | 2019-12-03 |
| 10409763 | Apparatus and method for efficiently implementing a processor pipeline | Patrick P. Lai, Ethan Schuchman, David Keppel, Denis M. Khartikov, Polychronis Xekalakis +7 more | 2019-09-10 |
| 10338927 | Method and apparatus for implementing a dynamic out-of-order processor pipeline | Denis M. Khartikov, Naveen Neelakantam, Polychronis Xekalakis | 2019-07-02 |
| 10055369 | Systems and methods for coalescing interrupts | Charles E. Tucker, Erik P. Machnicki, Fan Wu | 2018-08-21 |
| 9971599 | Instruction and logic for support of code modification | David Keppel, David N. Mackintosh | 2018-05-15 |
| 9870209 | Instruction and logic for reducing data cache evictions in an out-of-order processor | Demos Pavlou, Mirem Hyuseinova | 2018-01-16 |
| 9652268 | Instruction and logic for support of code modification | David Keppel, David N. Mackintosh | 2017-05-16 |
| 9612840 | Method and apparatus for implementing a dynamic out-of-order processor pipeline | Denis M. Khartikov, Naveen Neelakantam, Polychronis Xekalakis | 2017-04-04 |
| 9569212 | Instruction and logic for a memory ordering buffer | Denis M. Khartikov, Naveen Neelakantam | 2017-02-14 |
| 9471292 | Binary translation reuse in a system with address space layout randomization | David N. Mackintosh, Neil A. Campbell | 2016-10-18 |
| 9256497 | Checkpoints associated with an out of order architecture | Denis M. Khartikov, Naveen Neelakantam | 2016-02-09 |