Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Polychronis Xekalakis — 17 Patents

Intel: 16 patents #2,596 of 30,777Top 9%
Overall (All Time): #263,971 of 4,157,543Top 7%
17 Patents All Time
Polychronis Xekalakis has been granted 17 US patents while listed as an inventor at Intel. The first was granted in 2017 and the most recent in December 2025. Polychronis Xekalakis ranks #263,971 of 4,157,543 US inventors in our database (top 6.3%). Patent records list Polychronis Xekalakis in Barcelona, CA, ES.

Patents per Year

Patents granted per year, 2017 to 2025Bar chart with a peak of 5 patents in 2017.peak 52017: 5 patents20172018: 3 patents20182019: 4 patents20192020: 3 patents20202025: 2 patents2025

Issued Patents All Time

Showing 1–17 of 17 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12511127 Dynamic reconfiguration of a multi-core processor to a unified core Samuel Charles Tsen, Jr., David T. Hass, Guillermo J. Rozas, Yusuf Cagatay Tekmen, Nickolas Andrew Fortino +4 more 2025-12-30
12248785 Instruction length decoding Sumit Ahuja 2025-03-11
10795681 Instruction length decoding Sumit Ahuja 2020-10-06 $29,609,000
10635465 Apparatuses and methods to prevent execution of a modified instruction Jamison D. Collins, Jason M. Agron 2020-04-28 $36,717,000
10545735 Apparatus and method for efficient call/return emulation using a dual return stack buffer Jason M. Agron 2020-01-28 $38,246,000
10409763 Apparatus and method for efficiently implementing a processor pipeline Patrick P. Lai, Ethan Schuchman, David Keppel, Denis M. Khartikov, Joshua B. Fryman +7 more 2019-09-10 $24,704,000
10387159 Apparatus and method for architectural performance monitoring in binary translation systems Jason M. Agron, Paul Caprioli, Jiwei Lu, Koichi Yamada 2019-08-20 $17,708,000
10338927 Method and apparatus for implementing a dynamic out-of-order processor pipeline Denis M. Khartikov, Naveen Neelakantam, John H. Kelm 2019-07-02 $19,690,000
10324724 Hardware apparatuses and methods to fuse instructions Patrick P. Lai, Tyler Sondag, Sebastian Winkel, Ethan Schuchman, Jayesh Iyer 2019-06-18 $21,210,000
10157063 Instruction and logic for optimization level aware branch prediction Pedro Marcuello, Alejandro Vicente Martinez, Christos E. Kotselidis, Grigorios Magklis, Fernando Latorre +13 more 2018-12-18 $25,622,000
10061587 Instruction and logic for bulk register reclamation David Keppel, Denis M. Khartikov, Fernando Latorre, Marc Lupon, Grigorios Magklis +2 more 2018-08-28 $28,989,000
10013326 Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region Raul Martinez, Enric Gibert Codina, Pedro Lopez, Marti Torrents Lapuerta, Georgios Tournavitis +14 more 2018-07-03 $24,450,000
9823938 Providing deterministic, reproducible, and random sampling in a processor Girish Venkatasubramanian, Jamison D. Collins, Jason M. Agron 2017-11-21 $11,290,000
9817642 Apparatus and method for efficient call/return emulation using a dual return stack buffer Jason M. Agron 2017-11-14 $11,178,000
9811341 Managed instruction cache prefetching Kyriakos A. Stavrou, Enric Gibert Codina, Josep M. Codina, Crispin Gomez Requena, Antonio Gonzalez +13 more 2017-11-07 $13,901,000
9710389 Method and apparatus for memory aliasing detection in an out-of-order instruction execution platform Oleg Margulis, Sumit Ahuja, Yongjun Park, Vineeth Mekkat, Igor Yanover +2 more 2017-07-18 $6,909,000
9612840 Method and apparatus for implementing a dynamic out-of-order processor pipeline Denis M. Khartikov, Naveen Neelakantam, John H. Kelm 2017-04-04 $8,141,000