| 11803389 |
Reach matrix scheduler circuit for scheduling instructions to be executed in a processor |
Rodney Wayne Smith, Douglas C. Burger, Gagan Gupta, Kiran Ravi Seth |
2023-10-31 |
| 11669333 |
Method, apparatus, and system for reducing live readiness calculations in reservation stations |
Rodney Wayne Smith, Raghavan MADHAVAN, Luke Yen, Shivam Priyadarshi |
2023-06-06 |
| 11593117 |
Combining load or store instructions |
Harsh Thakker, Thomas Philip Speier, Rodney Wayne Smith, Kevin JAGET, James Norris Dieffenderfer +5 more |
2023-02-28 |
| 11392410 |
Operand pool instruction reservation clustering in a scheduler circuit in a processor |
Shivam Priyadarshi, Rodney Wayne Smith, Vignyan Reddy Kothinti Naresh |
2022-07-19 |
| 11327763 |
Opportunistic consumer instruction steering based on producer instruction value prediction in a multi-cluster processor |
Arthur Perais, Shivam Priyadarshi, Rami Mohammad Al Sheikh, Vignyan Reddy Kothinti Naresh |
2022-05-10 |
| 11113068 |
Performing flush recovery using parallel walks of sliced reorder buffers (SROBs) |
Rodney Wayne Smith, Kiran Ravi Seth, Shivam Priyadarshi |
2021-09-07 |
| 11061677 |
Recovering register mapping state of a flushed instruction employing a snapshot of another register mapping state and traversing reorder buffer (ROB) entries in a processor |
Kiran Ravi Seth, Rodney Wayne Smith, Shivam Priyadarshi, Vignyan Reddy Kothinti Naresh |
2021-07-13 |
| 11023243 |
Latency-based instruction reservation station clustering in a scheduler circuit in a processor |
Shivam Priyadarshi, Rodney Wayne Smith |
2021-06-01 |
| 10956162 |
Operand-based reach explicit dataflow processors, and related methods and computer-readable media |
Robert Douglas Clancy, Melinda J. Brown, Brian Michael Stempel, Michael Scott McIlvaine, Thomas Philip Speier +3 more |
2021-03-23 |
| 10896041 |
Enabling early execution of move-immediate instructions having variable immediate value sizes in processor-based devices |
Shivam Priyadarshi, Arthur Perais, Vignyan Reddy Kothinti Naresh, Rami Mohammad Al Sheikh, Rodney Wayne Smith |
2021-01-19 |
| 10877768 |
Minimizing traversal of a processor reorder buffer (ROB) for register rename map table (RMT) state recovery for interrupted instruction recovery in a processor |
Shivam Priyadarshi, Kiran Ravi Seth, Rodney Wayne Smith, Vignyan Reddy Kothinti Naresh |
2020-12-29 |
| 10860328 |
Providing late physical register allocation and early physical register release in out-of-order processor (OOP)-based devices implementing a checkpoint-based architecture |
Shivam Priyadarshi, Rodney Wayne Smith, Luke Yen |
2020-12-08 |
| 10514921 |
Fast reuse of physical register names |
Tejaswi Talluru, Rodney Wayne Smith, Kiran Ravi Seth, Daniel Higdon, Jeffery M. Schottmiller +1 more |
2019-12-24 |
| 9304774 |
Processor with a coprocessor having early access to not-yet issued instructions |
Kenneth Alan Dockser |
2016-04-05 |
| 9164772 |
Hybrid queue for storing instructions from fetch queue directly in out-of-order queue or temporarily in in-order queue until space is available |
Kenneth Alan Dockser |
2015-10-20 |
