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Processor branch prediction circuit employing back-invalidation of prediction cache entries based on decoded branch instructions and related methods |
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Operand-based reach explicit dataflow processors, and related methods and computer-readable media |
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Branch prediction based on load-path history |
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2020-11-17 |
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Precise invalidation of virtually tagged caches |
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2019-06-11 |
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Preventing the displacement of high temporal locality of reference data fill buffers |
Thomas Philip Speier, James Norris Dieffenderfer |
2018-10-30 |
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Determining cache hit/miss of aliased addresses in virtually-tagged cache(s), and related systems and methods |
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Method for filtering traffic to a physically-tagged data cache |
James Norris Dieffenderfer, Thomas Philip Speier |
2013-12-17 |
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Latency insensitive FIFO signaling protocol |
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2010-05-25 |
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Method and apparatus for managing cache partitioning using a dynamic boundary |
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2010-01-19 |
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Latency insensitive FIFO signaling protocol |
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2008-11-18 |
