| 8661229 |
Power efficient instruction prefetch mechanism |
Thomas Andrew Sartorius, James Norris Dieffenderfer, Jeffrey Todd Bridges, Michael Scott McIlvaine, Rodney Wayne Smith |
2014-02-25 |
| 8527713 |
Cache locking without interference from normal allocations |
James Norris Dieffenderfer, Jeffrey Todd Bridges, Thomas Andrew Sartorius |
2013-09-03 |
| 8239657 |
Address translation method and apparatus |
Brian Joseph Kopec, James Norris Dieffenderfer, Thomas Andrew Sartorius |
2012-08-07 |
| 7725625 |
Latency insensitive FIFO signaling protocol |
Kenneth Alan Dockser, James Norris Dieffenderfer, Jeffrey Todd Bridges, Robert Douglas Clancy, Thomas Andrew Sartorius |
2010-05-25 |
| 7725684 |
Speculative instruction issue in a simultaneously multithreaded processor |
Jeffrey Todd Bridges, Michael Scott McIlvaine, Thomas Andrew Sartorius, Rodney Wayne Smith |
2010-05-25 |
| 7721067 |
Translation lookaside buffer manipulation |
Brian Joseph Kopec, James Norris Dieffenderfer, Jeffrey Todd Bridges, Thomas Andrew Sartorius |
2010-05-18 |
| 7650466 |
Method and apparatus for managing cache partitioning using a dynamic boundary |
Brian Michael Stempel, James Norris Dieffenderfer, Jeffrey Todd Bridges, Thomas Andrew Sartorius, Rodney Wayne Smith +1 more |
2010-01-19 |
| 7587580 |
Power efficient instruction prefetch mechanism |
Thomas Andrew Sartorius, James Norris Dieffenderfer, Jeffrey Todd Bridges, Michael Scott McIlvaine, Rodney Wayne Smith |
2009-09-08 |
| 7454538 |
Latency insensitive FIFO signaling protocol |
Kenneth Alan Dockser, James Norris Dieffenderfer, Jeffrey Todd Bridges, Robert Douglas Clancy, Thomas Andrew Sartorius |
2008-11-18 |
| 7437537 |
Methods and apparatus for predicting unaligned memory access |
Jeffrey Todd Bridges, James Norris Dieffenderfer, Thomas Andrew Sartorius |
2008-10-14 |
| 7426626 |
TLB lock indicator |
James Norris Dieffenderfer, Jeffrey Todd Bridges, Thomas Andrew Sartorius |
2008-09-16 |
| 7366877 |
Speculative instruction issue in a simultaneously multithreaded processor |
Jeffrey Todd Bridges, Michael Scott McIlvaine, Thomas Andrew Sartorius, Rodney Wayne Smith |
2008-04-29 |
| 7366869 |
Method and system for optimizing translation lookaside buffer entries |
Thomas Andrew Sartorius, Jeffrey Todd Bridges, James Norris Dieffenderfer |
2008-04-29 |
| 7330941 |
Global modified indicator to reduce power consumption on cache miss |
Thomas Andrew Sartorius, James Norris Dieffenderfer |
2008-02-12 |
| 7296175 |
System on a chip bus with automatic pipeline stage insertion for timing closure |
James Norris Dieffenderfer, Bernard C. Drerup, Richard Gerard Hofmann, Thomas Andrew Sartorius, Barry Joe Wolford |
2007-11-13 |
| 7035958 |
Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the target |
James Norris Dieffenderfer, Bernard C. Drerup, Richard Gerard Hofmann, Thomas Andrew Sartorius, Barry Joe Wolford |
2006-04-25 |
| 6948053 |
Efficiently calculating a branch target address |
Jeffrey Todd Bridges, Thomas Andrew Sartorius, Rodney Wayne Smith, Thomas Philip Speier |
2005-09-20 |
| 6907502 |
Method for moving snoop pushes to the front of a request queue |
James Norris Dieffenderfer, Bernard C. Drerup, Jaya Prakash Subramaniam Ganasan, Richard Gerard Hofmann, Thomas Andrew Sartorius +2 more |
2005-06-14 |
| 6834378 |
System on a chip bus with automatic pipeline stage insertion for timing closure |
James Norris Dieffenderfer, Bernard C. Drerup, Richard Gerard Hofmann, Thomas Andrew Sartorius, Barry Joe Wolford |
2004-12-21 |
| 6826747 |
System and method for tracing program instructions before and after a trace triggering event within a processor |
Jeffrey Todd Bridges, Thomas Kevin Collopy, James Norris Dieffenderfer, Thomas Andrew Sartorius |
2004-11-30 |
| 6826656 |
Reducing power in a snooping cache based multiprocessor environment |
James Norris Dieffenderfer, Bernard C. Drerup, Richard Gerard Hofmann, Thomas Andrew Sartorius, Barry Joe Wolford |
2004-11-30 |
| 6816962 |
Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions |
Jeffrey Todd Bridges, Thomas Andrew Sartorius, Rodney Wayne Smith, Thomas Philip Speier |
2004-11-09 |
| 6807608 |
Multiprocessor environment supporting variable-sized coherency transactions |
James Norris Dieffenderfer, Bernard C. Drerup, Richard Gerard Hofmann, Thomas Andrew Sartorius, Barry Joe Wolford |
2004-10-19 |
| 6513134 |
System and method for tracing program execution within a superscalar processor |
Jeffrey Todd Bridges, Thomas Andrew Sartorius, Rodney Wayne Smith |
2003-01-28 |
| 5996092 |
System and method for tracing program execution within a processor before and after a triggering event |
Jeffrey Todd Bridges, Thomas Kevin Collopy, James Norris Dieffenderfer, Thomas Andrew Sartorius |
1999-11-30 |
