Issued Patents All Time
Showing 25 most recent of 70 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11842196 | Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions | Thomas Andrew Sartorius, Thomas Philip Speier, Michael Scott McIlvaine, James Norris Dieffenderfer | 2023-12-12 |
| 11803389 | Reach matrix scheduler circuit for scheduling instructions to be executed in a processor | Yusuf Cagatay Tekmen, Douglas C. Burger, Gagan Gupta, Kiran Ravi Seth | 2023-10-31 |
| 11669333 | Method, apparatus, and system for reducing live readiness calculations in reservation stations | Raghavan MADHAVAN, Luke Yen, Shivam Priyadarshi, Yusuf Cagatay Tekmen | 2023-06-06 |
| 11593117 | Combining load or store instructions | Harsh Thakker, Thomas Philip Speier, Kevin JAGET, James Norris Dieffenderfer, Michael William Morrow +5 more | 2023-02-28 |
| 11392537 | Reach-based explicit dataflow processors, and related computer-readable media and methods | Gagan Gupta, Michael Scott McIlvaine, Thomas Philip Speier, David T. Harper | 2022-07-19 |
| 11392410 | Operand pool instruction reservation clustering in a scheduler circuit in a processor | Shivam Priyadarshi, Yusuf Cagatay Tekmen, Vignyan Reddy Kothinti Naresh | 2022-07-19 |
| 11188334 | Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions | Thomas Andrew Sartorius, Thomas Philip Speier, Michael Scott McIlvaine, James Norris Dieffenderfer | 2021-11-30 |
| 11113068 | Performing flush recovery using parallel walks of sliced reorder buffers (SROBs) | Yusuf Cagatay Tekmen, Kiran Ravi Seth, Shivam Priyadarshi | 2021-09-07 |
| 11061677 | Recovering register mapping state of a flushed instruction employing a snapshot of another register mapping state and traversing reorder buffer (ROB) entries in a processor | Kiran Ravi Seth, Yusuf Cagatay Tekmen, Shivam Priyadarshi, Vignyan Reddy Kothinti Naresh | 2021-07-13 |
| 11036512 | Systems and methods for processing instructions having wide immediate operands | Arthur Perais, Shivam Priyadarshi, Rami Mohammad Al Sheikh, Vignyan Reddy Kothinti Naresh | 2021-06-15 |
| 11023243 | Latency-based instruction reservation station clustering in a scheduler circuit in a processor | Yusuf Cagatay Tekmen, Shivam Priyadarshi | 2021-06-01 |
| 10956162 | Operand-based reach explicit dataflow processors, and related methods and computer-readable media | Robert Douglas Clancy, Melinda J. Brown, Yusuf Cagatay Tekmen, Brian Michael Stempel, Michael Scott McIlvaine +3 more | 2021-03-23 |
| 10896041 | Enabling early execution of move-immediate instructions having variable immediate value sizes in processor-based devices | Shivam Priyadarshi, Arthur Perais, Vignyan Reddy Kothinti Naresh, Yusuf Cagatay Tekmen, Rami Mohammad Al Sheikh | 2021-01-19 |
| 10877768 | Minimizing traversal of a processor reorder buffer (ROB) for register rename map table (RMT) state recovery for interrupted instruction recovery in a processor | Shivam Priyadarshi, Yusuf Cagatay Tekmen, Kiran Ravi Seth, Vignyan Reddy Kothinti Naresh | 2020-12-29 |
| 10860328 | Providing late physical register allocation and early physical register release in out-of-order processor (OOP)-based devices implementing a checkpoint-based architecture | Shivam Priyadarshi, Yusuf Cagatay Tekmen, Luke Yen | 2020-12-08 |
| 10551896 | Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase | Shivam Priyadarshi, Anil Krishna, Raguram Damodaran, Jeffrey Todd Bridges, Ryan D. Wells +1 more | 2020-02-04 |
| 10514921 | Fast reuse of physical register names | Tejaswi Talluru, Yusuf Cagatay Tekmen, Kiran Ravi Seth, Daniel Higdon, Jeffery M. Schottmiller +1 more | 2019-12-24 |
| 10108417 | Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor | Anil Krishna, Sandeep Suresh Navada, Shivam Priyadarshi, Raguram Damodaran | 2018-10-23 |
| 9851774 | Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase | Shivam Priyadarshi, Anil Krishna, Raguram Damodaran, Jeffrey Todd Bridges, Ryan D. Wells +1 more | 2017-12-26 |
| 9823929 | Optimizing performance for context-dependent instructions | Daren Eugene Streett, Brian Michael Stempel, Thomas Philip Speier, Michael Scott McIlvaine, Kenneth Alan Dockser +1 more | 2017-11-21 |
| 9477476 | Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media | Melinda J. Brown, Michael William Morrow, James Norris Dieffenderfer, Brian Michael Stempel, Michael Scott McIlvaine +2 more | 2016-10-25 |
| 9471325 | Method and apparatus for selective renaming in a microprocessor | Anil Krishna, Sandeep Suresh Navada, Niket K. Choudhary, Michael Scott McIlvaine, Thomas Andrew Sartorius +1 more | 2016-10-18 |
| 9411590 | Method to improve speed of executing return branch instructions in a processor | Jeffery M. Schottmiller, Michael Scott McIlvaine, Brian Michael Stempel, Melinda J. Brown, Daren Eugene Streett | 2016-08-09 |
| 9195466 | Fusing conditional write instructions having opposite conditions in instruction processing circuits, and related processor systems, methods, and computer-readable media | Melinda J. Brown, James Norris Dieffenderfer, Michael Scott McIlvaine, Brian Michael Stempel, Jeffery M. Schottmiller +2 more | 2015-11-24 |
| 8943300 | Method and apparatus for generating return address predictions for implicit and explicit subroutine calls using predecode information | Brian Michael Stempel, James Norris Dieffenderfer, Thomas Andrew Sartorius | 2015-01-27 |