Issued Patents All Time
Showing 26–50 of 70 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8898437 | Predecode repair cache for instructions that cross an instruction cache line | Brian Michael Stempel, David John Mandzak, James Norris Dieffenderfer | 2014-11-25 |
| 8661229 | Power efficient instruction prefetch mechanism | Thomas Andrew Sartorius, Victor Roberts Augsburg, James Norris Dieffenderfer, Jeffrey Todd Bridges, Michael Scott McIlvaine | 2014-02-25 |
| 8438372 | Link stack repair of erroneous speculative update | James Norris Dieffenderfer, Brian Michael Stempel | 2013-05-07 |
| 8438371 | Link stack repair of erroneous speculative update | James Norris Dieffenderfer, Brian Michael Stempel | 2013-05-07 |
| 8352713 | Debug circuit comparing processor instruction set operating mode | Kevin Charles Burke, Brian Michael Stempel, Daren Eugene Streett, Kevin Allen Sapp, Leslie Mark DeBruyne +2 more | 2013-01-08 |
| 8185725 | Selective powering of a BHT in a processor having variable length instructions | Brian Michael Stempel | 2012-05-22 |
| 8145883 | Preloading instructions from an instruction set other than a currently executing instruction set | Thomas Andrew Sartorius, Brian Michael Stempel | 2012-03-27 |
| 8082428 | Methods and system for resolving simultaneous predicted branch instructions | Brian Michael Stempel, James Norris Dieffenderfer, Thomas Andrew Sartorius | 2011-12-20 |
| 7984279 | System and method for using a working global history register | Brian Michael Stempel, James Norris Dieffenderfer, Thomas Andrew Sartorius | 2011-07-19 |
| 7971044 | Link stack repair of erroneous speculative update | James Norris Dieffenderfer, Brian Michael Stempel | 2011-06-28 |
| 7962725 | Pre-decoding variable length instructions | Brian Michael Stempel | 2011-06-14 |
| 7917731 | Method and apparatus for prefetching non-sequential instruction addresses | Brian Michael Stempel, Thomas Andrew Sartorius | 2011-03-29 |
| 7827392 | Sliding-window, block-based branch target address cache | James Norris Dieffenderfer, Thomas Andrew Sartorius, Brian Michael Stempel | 2010-11-02 |
| 7805588 | Caching memory attribute indicators with cached memory data field | Jeffrey Todd Bridges, James Norris Dieffenderfer, Thomas Andrew Sartorius, Brian Michael Stempel | 2010-09-28 |
| 7802055 | Virtually-tagged instruction cache with physically-tagged behavior | Thomas Andrew Sartorius, Daren Eugene Streett | 2010-09-21 |
| 7793079 | Method and system for expanding a conditional instruction into a unconditional instruction and a select instruction | Serena Badran-Louca, Michael Scott McIlvaine | 2010-09-07 |
| 7769983 | Caching instructions for a multiple-state processor | Brian Michael Stempel | 2010-08-03 |
| 7725684 | Speculative instruction issue in a simultaneously multithreaded processor | Victor Roberts Augsburg, Jeffrey Todd Bridges, Michael Scott McIlvaine, Thomas Andrew Sartorius | 2010-05-25 |
| 7716460 | Effective use of a BHT in processor having variable length instruction set execution modes | Brian Michael Stempel | 2010-05-11 |
| 7711927 | System, method and software to preload instructions from an instruction set other than one currently executing | Thomas Andrew Sartorius, Brian Michael Stempel | 2010-05-04 |
| 7681022 | Efficient interrupt return address save mechanism | Thomas Andrew Sartorius, Michael Scott McIlvaine | 2010-03-16 |
| 7676659 | System, method and software to preload instructions from a variable-length instruction set with proper pre-decoding | Brian Michael Stempel, Thomas Andrew Sartorius | 2010-03-09 |
| 7669039 | Use of register renaming system for forwarding intermediate results between constituent instructions of an expanded instruction | Michael Scott McIlvaine, James Norris Dieffenderfer, Nathan Samuel Nunamaker, Thomas Andrew Sartorius | 2010-02-23 |
| 7650466 | Method and apparatus for managing cache partitioning using a dynamic boundary | Brian Michael Stempel, James Norris Dieffenderfer, Jeffrey Todd Bridges, Thomas Andrew Sartorius, Robert Douglas Clancy +1 more | 2010-01-19 |
| 7624254 | Segmented pipeline flushing for mispredicted branches | James Norris Dieffenderfer, Michael Scott McIlvaine, Thomas Andrew Sartorius | 2009-11-24 |