| 12260220 |
Accelerating fetch target queue (FTQ) processing in a processor |
Saransh JAIN, Rami Mohammad Al Sheikh, Michael Scott McIlvaine, Somasundaram Arunachalam |
2025-03-25 |
| 12229568 |
Methods and circuitry for efficient management of local branch history registers |
Rami Mohammad Al Sheikh, Ahmed Abulila, Michael Scott McIlvaine |
2025-02-18 |
| 12086600 |
Branch target buffer with shared target bits |
Somasundaram Arunachalam, Richard W. Doing |
2024-09-10 |
| 11995443 |
Reuse of branch information queue entries for multiple instances of predicted control instructions in captured loops in a processor |
Rami Mohammad Al Sheikh |
2024-05-28 |
| 11928474 |
Selectively updating branch predictors for loops executed from loop buffers in a processor |
Rami Mohammad Al Sheikh, Saransh JAIN, Michael Scott McIlvaine |
2024-03-12 |
| 11915002 |
Providing extended branch target buffer (BTB) entries for storing trunk branch metadata and leaf branch metadata |
Saransh JAIN, Rami Mohammad Al Sheikh, Michael Scott McIlvaine |
2024-02-27 |
| 11789740 |
Performing branch predictor training using probabilistic counter updates in a processor |
Rami Mohammad Al Sheikh, Michael Scott McIlvaine |
2023-10-17 |
| 11768688 |
Methods and circuitry for efficient management of local branch history registers |
Rami Mohammad Al Sheikh, Ahmed Abulila, Michael Scott McIlvaine |
2023-09-26 |
| 11487545 |
Processor branch prediction circuit employing back-invalidation of prediction cache entries based on decoded branch instructions and related methods |
Rami Mohammad Al Sheikh, Michael Scott McIlvaine, Richard W. Doing, Robert Douglas Clancy |
2022-11-01 |
| 9823929 |
Optimizing performance for context-dependent instructions |
Brian Michael Stempel, Thomas Philip Speier, Rodney Wayne Smith, Michael Scott McIlvaine, Kenneth Alan Dockser +1 more |
2017-11-21 |
| 9477478 |
Multi level indirect predictor using confidence counter and program counter address filter scheme |
Kulin N. Kothari, Michael William Morrow, James Norris Dieffenderfer, Michael Scott McIlvaine, Brian Michael Stempel |
2016-10-25 |
| 9411590 |
Method to improve speed of executing return branch instructions in a processor |
Rodney Wayne Smith, Jeffery M. Schottmiller, Michael Scott McIlvaine, Brian Michael Stempel, Melinda J. Brown |
2016-08-09 |
| 9317293 |
Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce execution pipeline bubbles, and related systems, methods, and computer-readable media |
James Norris Dieffenderfer, Michael William Morrow, Michael Scott McIlvaine, Vimal Reddy, Brian Michael Stempel |
2016-04-19 |
| 8352713 |
Debug circuit comparing processor instruction set operating mode |
Kevin Charles Burke, Brian Michael Stempel, Kevin Allen Sapp, Leslie Mark DeBruyne, Nabil Amir Rizk +2 more |
2013-01-08 |
| 8291202 |
Apparatus and methods for speculative interrupt vector prefetching |
Brian Michael Stempel |
2012-10-16 |
| 7802055 |
Virtually-tagged instruction cache with physically-tagged behavior |
Thomas Andrew Sartorius, Rodney Wayne Smith |
2010-09-21 |
