Issued Patents All Time
Showing 25 most recent of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11864539 | Aquaculture systems and methods | Johan Perslow, Andrew Komor | 2024-01-09 |
| 11593117 | Combining load or store instructions | Harsh Thakker, Thomas Philip Speier, Rodney Wayne Smith, Kevin JAGET, James Norris Dieffenderfer +5 more | 2023-02-28 |
| 10855674 | Pre-boot network-based authentication | Darrell Geusz, Loic Fabro | 2020-12-01 |
| 10709117 | Aquaculture systems and methods | Johan Perslow, Andrew Komor | 2020-07-14 |
| 9858077 | Issuing instructions to execution pipelines based on register-associated preferences, and related instruction processing circuits, processor systems, methods, and computer-readable media | Melinda J. Brown, James Norris Dieffenderfer, Brian Michael Stempel, Michael Scott McIlvaine | 2018-01-02 |
| 9514061 | Method and apparatus for cache tag compression | Henry A. Pellerin, Thomas Philip Speier, Thomas Andrew Sartorius, James Norris Dieffenderfer, Kenneth Alan Dockser +1 more | 2016-12-06 |
| 9477476 | Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media | Melinda J. Brown, James Norris Dieffenderfer, Brian Michael Stempel, Michael Scott McIlvaine, Rodney Wayne Smith +2 more | 2016-10-25 |
| 9477478 | Multi level indirect predictor using confidence counter and program counter address filter scheme | Kulin N. Kothari, James Norris Dieffenderfer, Michael Scott McIlvaine, Brian Michael Stempel, Daren Eugene Streett | 2016-10-25 |
| 9430385 | Moveable locked lines in a multi-level cache | Dennis M. O'Connor, Stephen Strazdus | 2016-08-30 |
| 9317293 | Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce execution pipeline bubbles, and related systems, methods, and computer-readable media | James Norris Dieffenderfer, Michael Scott McIlvaine, Daren Eugene Streett, Vimal Reddy, Brian Michael Stempel | 2016-04-19 |
| 9195466 | Fusing conditional write instructions having opposite conditions in instruction processing circuits, and related processor systems, methods, and computer-readable media | Melinda J. Brown, James Norris Dieffenderfer, Michael Scott McIlvaine, Brian Michael Stempel, Rodney Wayne Smith +2 more | 2015-11-24 |
| 9146607 | Methods and apparatus to selectively power functional units | Dennis M. O'Connor, Lawrence T. Clark | 2015-09-29 |
| 9146741 | Eliminating redundant masking operations instruction processing circuits, and related processor systems, methods, and computer-readable media | Melinda J. Brown, James Norris Dieffenderfer, Brian Michael Stempel, Michael Scott McIlvaine | 2015-09-29 |
| 9092358 | Memory management unit with pre-filling capability | Bohuslav Rychlik, Thomas Andrew Sartorius, Raymond P. Palma | 2015-07-28 |
| 9043795 | Apparatus and methods for adaptive thread scheduling on asymmetric multiprocessor | Manish Garg | 2015-05-26 |
| 8932996 | Gas hydrate inhibitors and methods for making and using same | Olusegun Matthew Falana, Frank Zamora | 2015-01-13 |
| 8856448 | Methods and apparatus for low intrusion snoop invalidation | James Norris Dieffenderfer | 2014-10-07 |
| 8732490 | Methods and apparatus to selectively power functional units | Dennis M. O'Connor, Lawrence T. Clark | 2014-05-20 |
| 8533395 | Moveable locked lines in a multi-level cache | Dennis M. O'Connor, Stephen Strazdus | 2013-09-10 |
| 8341383 | Method and a system for accelerating procedure return sequences | James Norris Dieffenderfer | 2012-12-25 |
| 8112643 | Methods and apparatus to selectively power functional units | Dennis M. O'Connor, Lawrence T. Clark | 2012-02-07 |
| 8060701 | Apparatus and methods for low-complexity instruction prefetch system | James Norris Dieffenderfer | 2011-11-15 |
| 7987337 | Translation lookaside buffer prediction mechanism | Dennis M. O'Connor, Desikan Iyadurai | 2011-07-26 |
| 7949834 | Method and apparatus for setting cache policies in a processor | — | 2011-05-24 |
| 7917702 | Data prefetch throttle | James Norris Dieffenderfer | 2011-03-29 |