Issued Patents All Time
Showing 25 most recent of 118 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11842196 | Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions | Thomas Andrew Sartorius, Thomas Philip Speier, Michael Scott McIlvaine, Rodney Wayne Smith | 2023-12-12 |
| 11593117 | Combining load or store instructions | Harsh Thakker, Thomas Philip Speier, Rodney Wayne Smith, Kevin JAGET, Michael William Morrow +5 more | 2023-02-28 |
| 11188334 | Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions | Thomas Andrew Sartorius, Thomas Philip Speier, Michael Scott McIlvaine, Rodney Wayne Smith | 2021-11-30 |
| 11175926 | Providing exception stack management using stack panic fault exceptions in processor-based devices | Thomas Andrew Sartorius, Michael Scott McIlvaine, Aaron S. Giles | 2021-11-16 |
| 11126437 | Load instruction with final read indicator field to invalidate a buffer or cache entry storing the memory address holding load data | Thomas Andrew Sartorius, Thomas Philip Speier, Michael Scott McIlvaine | 2021-09-21 |
| 10114750 | Preventing the displacement of high temporal locality of reference data fill buffers | Robert Douglas Clancy, Thomas Philip Speier | 2018-10-30 |
| 10108419 | Dependency-prediction of instructions | Brian Michael Stempel, Michael Scott McIlvaine, Melinda J. Brown | 2018-10-23 |
| 9858077 | Issuing instructions to execution pipelines based on register-associated preferences, and related instruction processing circuits, processor systems, methods, and computer-readable media | Melinda J. Brown, Michael William Morrow, Brian Michael Stempel, Michael Scott McIlvaine | 2018-01-02 |
| 9823929 | Optimizing performance for context-dependent instructions | Daren Eugene Streett, Brian Michael Stempel, Thomas Philip Speier, Rodney Wayne Smith, Michael Scott McIlvaine +1 more | 2017-11-21 |
| 9710269 | Early conditional selection of an operand | Jeffrey Todd Bridges, Michael Scott McIlvaine, Thomas Andrew Sartorius | 2017-07-18 |
| 9514061 | Method and apparatus for cache tag compression | Henry A. Pellerin, Thomas Philip Speier, Thomas Andrew Sartorius, Michael William Morrow, Kenneth Alan Dockser +1 more | 2016-12-06 |
| 9477476 | Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media | Melinda J. Brown, Michael William Morrow, Brian Michael Stempel, Michael Scott McIlvaine, Rodney Wayne Smith +2 more | 2016-10-25 |
| 9477478 | Multi level indirect predictor using confidence counter and program counter address filter scheme | Kulin N. Kothari, Michael William Morrow, Michael Scott McIlvaine, Brian Michael Stempel, Daren Eugene Streett | 2016-10-25 |
| 9460018 | Method and apparatus for tracking extra data permissions in an instruction cache | Leslie Mark DeBruyne, Michael Scott McIlvaine, Brian Michael Stempel | 2016-10-04 |
| 9317293 | Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce execution pipeline bubbles, and related systems, methods, and computer-readable media | Michael William Morrow, Michael Scott McIlvaine, Daren Eugene Streett, Vimal Reddy, Brian Michael Stempel | 2016-04-19 |
| 9292442 | Methods and apparatus for improving performance of semaphore management sequences across a coherent bus | Thomas Philip Speier, Eric F. Robinson, Jaya Prakash Subramaniam Ganasan, Thomas Andrew Sartorius | 2016-03-22 |
| 9195466 | Fusing conditional write instructions having opposite conditions in instruction processing circuits, and related processor systems, methods, and computer-readable media | Melinda J. Brown, Michael Scott McIlvaine, Brian Michael Stempel, Rodney Wayne Smith, Jeffery M. Schottmiller +2 more | 2015-11-24 |
| 9146741 | Eliminating redundant masking operations instruction processing circuits, and related processor systems, methods, and computer-readable media | Melinda J. Brown, Michael William Morrow, Brian Michael Stempel, Michael Scott McIlvaine | 2015-09-29 |
| 9110830 | Determining cache hit/miss of aliased addresses in virtually-tagged cache(s), and related systems and methods | Robert Douglas Clancy, Thomas Philip Speier | 2015-08-18 |
| 9026744 | Enforcing strongly-ordered requests in a weakly-ordered processing | Richard Gerard Hofmann, Thomas Andrew Sartorius, Thomas Philip Speier, Jaya Prakash Subramaniam Ganasan, James Edward Sullivan, Jr. | 2015-05-05 |
| 8943300 | Method and apparatus for generating return address predictions for implicit and explicit subroutine calls using predecode information | Brian Michael Stempel, Thomas Andrew Sartorius, Rodney Wayne Smith | 2015-01-27 |
| 8904155 | Representing loop branches in a branch history register with multiple bits | Bohuslav Rychlik | 2014-12-02 |
| 8898437 | Predecode repair cache for instructions that cross an instruction cache line | Rodney Wayne Smith, Brian Michael Stempel, David John Mandzak | 2014-11-25 |
| 8856448 | Methods and apparatus for low intrusion snoop invalidation | Michael William Morrow | 2014-10-07 |
| 8819342 | Methods and apparatus for managing page crossing instructions with different cacheability | Leslie Mark DeBruyne, Michael Scott McIlvaine, Brian Michael Stempel | 2014-08-26 |