Issued Patents All Time
Showing 25 most recent of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12260220 | Accelerating fetch target queue (FTQ) processing in a processor | Saransh JAIN, Rami Mohammad Al Sheikh, Daren Eugene Streett, Somasundaram Arunachalam | 2025-03-25 |
| 12229568 | Methods and circuitry for efficient management of local branch history registers | Rami Mohammad Al Sheikh, Ahmed Abulila, Daren Eugene Streett | 2025-02-18 |
| 11928474 | Selectively updating branch predictors for loops executed from loop buffers in a processor | Rami Mohammad Al Sheikh, Saransh JAIN, Daren Eugene Streett | 2024-03-12 |
| 11915002 | Providing extended branch target buffer (BTB) entries for storing trunk branch metadata and leaf branch metadata | Saransh JAIN, Rami Mohammad Al Sheikh, Daren Eugene Streett | 2024-02-27 |
| 11842196 | Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions | Thomas Andrew Sartorius, Thomas Philip Speier, James Norris Dieffenderfer, Rodney Wayne Smith | 2023-12-12 |
| 11789740 | Performing branch predictor training using probabilistic counter updates in a processor | Rami Mohammad Al Sheikh, Daren Eugene Streett | 2023-10-17 |
| 11768688 | Methods and circuitry for efficient management of local branch history registers | Rami Mohammad Al Sheikh, Ahmed Abulila, Daren Eugene Streett | 2023-09-26 |
| 11755327 | Delivering immediate values by using program counter (PC)-relative load instructions to fetch literal data in processor-based devices | Melinda J. Brown | 2023-09-12 |
| 11726787 | Reusing fetched, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-fetching | Rami Mohammad Al Sheikh | 2023-08-15 |
| 11487545 | Processor branch prediction circuit employing back-invalidation of prediction cache entries based on decoded branch instructions and related methods | Daren Eugene Streett, Rami Mohammad Al Sheikh, Richard W. Doing, Robert Douglas Clancy | 2022-11-01 |
| 11392537 | Reach-based explicit dataflow processors, and related computer-readable media and methods | Gagan Gupta, Rodney Wayne Smith, Thomas Philip Speier, David T. Harper | 2022-07-19 |
| 11360773 | Reusing fetched, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-fetching | Rami Mohammad Al Sheikh | 2022-06-14 |
| 11334488 | Cache management circuits for predictive adjustment of cache control policies based on persistent, history-based cache control information | Rami Mohammad Al Sheikh, Arthur Perais | 2022-05-17 |
| 11188334 | Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions | Thomas Andrew Sartorius, Thomas Philip Speier, James Norris Dieffenderfer, Rodney Wayne Smith | 2021-11-30 |
| 11175926 | Providing exception stack management using stack panic fault exceptions in processor-based devices | Thomas Andrew Sartorius, James Norris Dieffenderfer, Aaron S. Giles | 2021-11-16 |
| 11126437 | Load instruction with final read indicator field to invalidate a buffer or cache entry storing the memory address holding load data | Thomas Andrew Sartorius, Thomas Philip Speier, James Norris Dieffenderfer | 2021-09-21 |
| 11074077 | Reusing executed, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-execution | Rami Mohammad Al Sheikh | 2021-07-27 |
| 11068273 | Swapping and restoring context-specific branch predictor states on context switches in a processor | Rami Mohammad Al Sheikh | 2021-07-20 |
| 10956162 | Operand-based reach explicit dataflow processors, and related methods and computer-readable media | Robert Douglas Clancy, Melinda J. Brown, Yusuf Cagatay Tekmen, Brian Michael Stempel, Thomas Philip Speier +3 more | 2021-03-23 |
| 10838731 | Branch prediction based on load-path history | Rami Mohammad Al Sheikh, Robert Douglas Clancy, Derek Robert Hower | 2020-11-17 |
| 10474462 | Dynamic pipeline throttling using confidence-based weighting of in-flight branch instructions | Shivam Priyadarshi, Rami Mohammad Al Sheikh, Raguram Damodaran, Jeffrey Todd Bridges | 2019-11-12 |
| 10318436 | Precise invalidation of virtually tagged caches | William James McAvoy, Brian Michael Stempel, Spencer E. Williams, Robert Douglas Clancy, Thomas Philip Speier | 2019-06-11 |
| 10108419 | Dependency-prediction of instructions | Brian Michael Stempel, James Norris Dieffenderfer, Melinda J. Brown | 2018-10-23 |
| 9858077 | Issuing instructions to execution pipelines based on register-associated preferences, and related instruction processing circuits, processor systems, methods, and computer-readable media | Melinda J. Brown, James Norris Dieffenderfer, Michael William Morrow, Brian Michael Stempel | 2018-01-02 |
| 9823929 | Optimizing performance for context-dependent instructions | Daren Eugene Streett, Brian Michael Stempel, Thomas Philip Speier, Rodney Wayne Smith, Kenneth Alan Dockser +1 more | 2017-11-21 |