Issued Patents All Time
Showing 25 most recent of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9823929 | Optimizing performance for context-dependent instructions | Daren Eugene Streett, Brian Michael Stempel, Thomas Philip Speier, Rodney Wayne Smith, Michael Scott McIlvaine +1 more | 2017-11-21 |
| 9753694 | Division and root computation with fast result formatting | Michael Thomas Dibrino, Pathik Sunil Lall | 2017-09-05 |
| 9514061 | Method and apparatus for cache tag compression | Henry A. Pellerin, Thomas Philip Speier, Thomas Andrew Sartorius, Michael William Morrow, James Norris Dieffenderfer +1 more | 2016-12-06 |
| 9471325 | Method and apparatus for selective renaming in a microprocessor | Anil Krishna, Sandeep Suresh Navada, Niket K. Choudhary, Michael Scott McIlvaine, Thomas Andrew Sartorius +1 more | 2016-10-18 |
| 9304774 | Processor with a coprocessor having early access to not-yet issued instructions | Yusuf Cagatay Tekmen | 2016-04-05 |
| 9164772 | Hybrid queue for storing instructions from fetch queue directly in out-of-order queue or temporarily in in-order queue until space is available | Yusuf Cagatay Tekmen | 2015-10-20 |
| 9146706 | Controlled-precision iterative arithmetic logic unit | — | 2015-09-29 |
| 8799627 | Software selectable adjustment of SIMD parallelism | — | 2014-08-05 |
| 8595279 | Floating-point processor with reduced power requirements for selectable subprecision | — | 2013-11-26 |
| 8566568 | Method and apparatus for executing processor instructions based on a dynamically alterable delay | Gerald Paul Michalak | 2013-10-22 |
| 8447800 | Mode-based multiply-add recoding for denormal operands | Pathik Sunil Lall | 2013-05-21 |
| 8200945 | Vector unit in a processor enabled to replicate data on a first portion of a data bus to primary and secondary registers | Siddhartha Chatterjee, Fred Gehrung Gustayson, Manish Gupta | 2012-06-12 |
| 8122231 | Software selectable adjustment of SIMD parallelism | — | 2012-02-21 |
| 8082287 | Pre-saturating fixed-point multiplier | Bonnie Sexton | 2011-12-20 |
| 7912887 | Mode-based multiply-add recoding for denormal operands | Pathik Sunil Lall | 2011-03-22 |
| 7836284 | Microprocessor with automatic selection of processing parallelism mode based on width data of instructions | — | 2010-11-16 |
| 7793072 | Vector execution unit to process a vector instruction by executing a first operation on a first set of operands and a second operation on a second set of operands | — | 2010-09-07 |
| 7725519 | Floating-point processor with selectable subprecision | — | 2010-05-25 |
| 7725625 | Latency insensitive FIFO signaling protocol | Victor Roberts Augsburg, James Norris Dieffenderfer, Jeffrey Todd Bridges, Robert Douglas Clancy, Thomas Andrew Sartorius | 2010-05-25 |
| 7694114 | Software selectable adjustment of SIMD parallelism | — | 2010-04-06 |
| 7624256 | System and method wherein conditional instructions unconditionally provide output | Thomas Andrew Sartorius, James Norris Dieffenderfer, Jeffrey Todd Bridges, Michael Scott McIlvaine, Rodney Wayne Smith | 2009-11-24 |
| 7454538 | Latency insensitive FIFO signaling protocol | Victor Roberts Augsburg, James Norris Dieffenderfer, Jeffrey Todd Bridges, Robert Douglas Clancy, Thomas Andrew Sartorius | 2008-11-18 |
| 7386747 | Method and system for reducing power consumption of a programmable processor | — | 2008-06-10 |
| 6029243 | Floating-point processor with operand-format precision greater than execution precision | Timothy Pontius | 2000-02-22 |
| 6006030 | Microprocessor with programmable instruction trap for deimplementing instructions | — | 1999-12-21 |