Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10664421 | Reordering responses in a high performance on-chip network | Jeremy Chan, Drew E. Wingard, Chien-Chun Chou, Herve Alexanian, Kevin L. Daberkow +1 more | 2020-05-26 |
| 10303628 | Reordering responses in a high performance on-chip network | Jeremy Chan, Drew E. Wingard, Chien-Chun Chou, Herve Alexanian, Kevin L. Daberkow +1 more | 2019-05-28 |
| 8294504 | Methods and systems related to a configurable delay counter used with variable frequency clocks | — | 2012-10-23 |
| 8078948 | Two-phase data-transfer protocol | Jens Roever | 2011-12-13 |
| 7187741 | Clock domain crossing FIFO | Robert L. Payne, David R. Evoy | 2007-03-06 |
| 7085950 | Parallel data communication realignment of data sent in multiple groups | Gregory Ehmann, D. C. Sessions | 2006-08-01 |
| 6996106 | High-speed interchip interface protocol | Robert L. Payne, David R. Evoy, George Spatz | 2006-02-07 |
| 6839862 | Parallel data communication having skew intolerant data groups | David R. Evoy, Gregory Ehmann | 2005-01-04 |
| 6665855 | Method and arrangement for rapid silicon prototyping | Robert L. Payne, Mark Bapst | 2003-12-16 |
| 6636166 | Parallel communication based on balanced data-bit encoding | D. C. Sessions, Robert J. Caesar, Jr., Ivan Svestka, David R. Evoy, Mark Johnson +1 more | 2003-10-21 |
| 6542855 | Selecting a cache design for a computer system using a model with a seed cache to generate a trace | — | 2003-04-01 |
| 6543030 | Computer-implemented conversion of combination-logic module for improving timing characteristics of incorporating integrated circuit design | Liewei Bao | 2003-04-01 |
| 6513105 | FIFO system with variable-width interface to host processor | — | 2003-01-28 |
| 6507887 | Binary data memory design with data stored in low-power sense | Gregory Ehmann | 2003-01-14 |
| 6467010 | Method and arrangement for passing data between a reference chip and an external bus | Mark Johnson | 2002-10-15 |
| 6347395 | Method and arrangement for rapid silicon prototyping | Robert L. Payne, Mark Bapst | 2002-02-12 |
| 6337893 | Non-power-of-two grey-code counter system having binary incrementer with counts distributed with bilateral symmetry | — | 2002-01-08 |
| 6314154 | Non-power-of-two Gray-code counter and binary incrementer therefor | — | 2001-11-06 |
| 6154803 | Method and arrangement for passing data between a reference chip and an external bus | Mark Johnson | 2000-11-28 |
| 6029243 | Floating-point processor with operand-format precision greater than execution precision | Kenneth Alan Dockser | 2000-02-22 |
| 5978437 | Binary counter system using bit-wise matches with maximum count | — | 1999-11-02 |