LB

Liewei Bao

TI Tilera: 6 patents #9 of 28Top 35%
BO Bfly Operations: 4 patents #36 of 88Top 45%
Philips: 3 patents #1,693 of 7,731Top 25%
NV NVIDIA: 2 patents #2,855 of 7,811Top 40%
BN Butterfly Network: 1 patents #37 of 46Top 85%
RA Rambus: 1 patents #410 of 549Top 75%
Overall (All Time): #269,211 of 4,157,543Top 7%
17
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12130391 Methods and apparatuses for azimuthal summing of ultrasound data Nevada J. Sanchez, Tyler S. Ralston 2024-10-29
11808897 Methods and apparatuses for azimuthal summing of ultrasound data Nevada J. Sanchez, Tyler S. Ralston 2023-11-07
11650301 Serial interface for parameter transfer in an ultrasound device Kailiang Chen, Tyler S. Ralston, Nevada J. Sanchez 2023-05-16
11154279 Transmit generator for controlling a multilevel pulser of an ultrasound device, and related methods and apparatus Kailiang Chen, Tyler S. Ralston, Nevada J. Sanchez 2021-10-26
10859687 Serial interface for parameter transfer in an ultrasound device Kailiang Chen, Tyler S. Ralston, Nevada J. Sanchez 2020-12-08
10282338 Configuring routing in mesh networks Ian Rudolf Bratt 2019-05-07
9753854 Memory controller load balancing with configurable striping domains 2017-09-05
9384165 Configuring routing in mesh networks Ian Rudolf Bratt 2016-07-05
9063825 Memory controller load balancing with configurable striping domains 2015-06-23
8886899 Managing memory requests based on priority 2014-11-11
8737392 Configuring routing in mesh networks Ian Rudolf Bratt 2014-05-27
8738860 Computing in parallel processing environments Patrick Robert Griffin, Mathew Hostetter, Anant Agarwal, Chyi-Chang Miao, Christopher D. Metcalf +15 more 2014-05-27
8151088 Configuring routing in mesh networks Ian Rudolf Bratt 2012-04-03
7370152 Memory controller with prefetching capability Steven C. Woo, Bradley A. May 2008-05-06
6708257 Buffering system bus for external-memory access 2004-03-16
6701422 Memory control system with incrementer for generating speculative addresses 2004-03-02
6543030 Computer-implemented conversion of combination-logic module for improving timing characteristics of incorporating integrated circuit design Timothy Pontius 2003-04-01