Issued Patents All Time
Showing 25 most recent of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11868281 | Artificial reality system having multi-bank, multi-port distributed shared memory | Alok Mathur, Ennio Salemi, Valerio Catalano | 2024-01-09 |
| 11681627 | Distributed temporal cache for Systems on a Chip | Sridhar Sharma | 2023-06-20 |
| 11474970 | Artificial reality system with inter-processor communication (IPC) | Jun Wang, Neeraj Upasani, Wojciech Stefan Powiertowski, Gregory Ehmann, Marco Brambilla +2 more | 2022-10-18 |
| 11409671 | Artificial reality system having multi-bank, multi-port distributed shared memory | Alok Mathur, Ennio Salemi, Valerio Catalano | 2022-08-09 |
| 11231769 | Sequencer-based protocol adapter | Gregory Ehmann | 2022-01-25 |
| 10921874 | Hardware-based operating point controller for circuit regions in an integrated circuit | Gregory Ehmann | 2021-02-16 |
| 10901490 | Operating point controller for circuit regions | Gregory Ehmann | 2021-01-26 |
| 10664421 | Reordering responses in a high performance on-chip network | Jeremy Chan, Chien-Chun Chou, Herve Alexanian, Kevin L. Daberkow, Harutyun Aslanyan +1 more | 2020-05-26 |
| 10303628 | Reordering responses in a high performance on-chip network | Jeremy Chan, Chien-Chun Chou, Herve Alexanian, Kevin L. Daberkow, Harutyun Aslanyan +1 more | 2019-05-28 |
| 10152112 | Power manager with a power switch arbitrator | Gregory Ehmann, Neal T. Wingen | 2018-12-11 |
| 10062422 | Various methods and apparatus for configurable mapping of address regions onto one or more aggregate targets | Chien-Chun Chou, Stephen W. Hamilton, Ian A. Swarbrick, Vida Vakilotojar | 2018-08-28 |
| 9495290 | Various methods and apparatus to support outstanding requests to multiple targets while maintaining transaction ordering | Chien-Chun Chou, Stephen W. Hamilton, Ian A. Swarbrick, Vida Vakilotojar | 2016-11-15 |
| 9405700 | Methods and apparatus for virtualization in an integrated circuit | — | 2016-08-02 |
| 9292436 | Various methods and apparatus to support transactions whose data address sequence within that transaction crosses an interleaved channel address boundary | Chien-Chun Chou, Stephen W. Hamilton, Ian A. Swarbrick, Vida Vakilotojar | 2016-03-22 |
| 8972995 | Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads | Krishnan Srinivasan, Ruben Khazhakyan, Harutyan Aslanyan, Chien-Chun Chou | 2015-03-03 |
| 8868941 | Apparatus and methods for an interconnect power manager | Doddaballapur N. Jayasimha, Stephen W. Hamilton | 2014-10-21 |
| 8504992 | Method and apparatus for establishing a quality of service model | Wolf-Dietrich Weber, Chien-Chun Chou | 2013-08-06 |
| 8484397 | Various methods and apparatus for a memory scheduler with an arbiter | Krishnan Srinivasan | 2013-07-09 |
| 8438320 | Various methods and apparatus for address tiling and channel interleaving throughout the integrated system | Krishnan Srinivasan, Chien-Chun Chou | 2013-05-07 |
| 8407433 | Interconnect implementing internal controls | Chien-Chun Chou, Stephen W. Hamilton, Ian A. Swarbrick, Vida Vakilotojar | 2013-03-26 |
| 8229723 | Performance software instrumentation and analysis for electronic design automation | Krishnan Srinivasan, Chien-Chun Chou | 2012-07-24 |
| 8190804 | Various methods and apparatus for a memory scheduler with an arbiter | Krishnan Srinivasan | 2012-05-29 |
| 8108648 | Various methods and apparatus for address tiling | Krishnan Srinivasan, Vida Vakilotojar, Chien-Chun Chou | 2012-01-31 |
| 8032329 | Method and system to monitor, debug, and analyze performance of an electronic design | Chien-Chun Chou, Stephen W. Hamilton, Pascal Chauvet | 2011-10-04 |
| 8032676 | Methods and apparatuses to manage bandwidth mismatches between a sending device and a receiving device | Glenn S. Vinogradov | 2011-10-04 |