Issued Patents All Time
Showing 25 most recent of 65 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411774 | Treating main memory as a collection of tagged cache lines for trace logging | Jordi Mola | 2025-09-09 |
| 12373350 | Cache-line retention hint information for conditional write instruction | Matthew James Horsnell, Andreas Lars Sandberg, Robin Alexander Emery, Eric Ola Harald Liljedahl | 2025-07-29 |
| 12164441 | Method, apparatus, and system for storing memory encryption realm key IDs | Darren Lasko, Roberto Avanzi, Harb Abdulhamid, Vikramjit Sethi | 2024-12-10 |
| 12093186 | Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PAs) in a processor-based system | Madhavan Thirukkurungudi Venkataraman | 2024-09-17 |
| 12093164 | Efficiently replacing software breakpoint instructions in processor-based devices | Leslie Mark DeBruyne, Pedro Teixeira | 2024-09-17 |
| 11868269 | Tracking memory block access frequency in processor-based devices | Andrew Joseph RUSHING | 2024-01-09 |
| 11842196 | Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions | Thomas Andrew Sartorius, Michael Scott McIlvaine, James Norris Dieffenderfer, Rodney Wayne Smith | 2023-12-12 |
| 11803482 | Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PAs) in a processor-based system | Madhavan Thirukkurungudi Venkataraman | 2023-10-31 |
| 11789874 | Method, apparatus, and system for storing memory encryption realm key IDs | Darren Lasko, Roberto Avanzi, Harb Abdulhamid, Vikramjit Sethi | 2023-10-17 |
| 11704253 | Performing speculative address translation in processor-based devices | Jason S. Wohlgemuth, Artur Klauser, Gagan Gupta, Cody Dean Hartwig, Abolade Gbadegesin | 2023-07-18 |
| 11687453 | Cache-based trace logging using tags in an upper-level cache | Jordi Mola | 2023-06-27 |
| 11593117 | Combining load or store instructions | Harsh Thakker, Rodney Wayne Smith, Kevin JAGET, James Norris Dieffenderfer, Michael William Morrow +5 more | 2023-02-28 |
| 11561896 | Cache-based trace logging using tags in an upper-level cache | Jordi Mola | 2023-01-24 |
| 11550723 | Method, apparatus, and system for memory bandwidth aware data prefetching | Niket K. Choudhary, David Scott Ray, Eric F. Robinson, Harold W. Cain, III, Nikhil Narendradev Sharma +3 more | 2023-01-10 |
| 11392537 | Reach-based explicit dataflow processors, and related computer-readable media and methods | Gagan Gupta, Michael Scott McIlvaine, Rodney Wayne Smith, David T. Harper | 2022-07-19 |
| 11366769 | Enabling peripheral device messaging via application portals in processor-based devices | Artur Klauser, Jason S. Wohlgemuth, Abolade Gbadegesin, Gagan Gupta, Soheil Ebadian +1 more | 2022-06-21 |
| 11232042 | Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PAs) in a processor-based system | Madhavan Thirukkurungudi Venkataraman | 2022-01-25 |
| 11226910 | Ticket based request flow control | Joseph Gerald McDonald, Garrett M. Drapala, Eric F. Robinson, Kevin N. Magill, Richard Gerard Hofmann | 2022-01-18 |
| 11188334 | Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions | Thomas Andrew Sartorius, Michael Scott McIlvaine, James Norris Dieffenderfer, Rodney Wayne Smith | 2021-11-30 |
| 11126437 | Load instruction with final read indicator field to invalidate a buffer or cache entry storing the memory address holding load data | Thomas Andrew Sartorius, Michael Scott McIlvaine, James Norris Dieffenderfer | 2021-09-21 |
| 11119770 | Performing atomic store-and-invalidate operations in processor-based devices | Eric F. Robinson | 2021-09-14 |
| 11061822 | Method, apparatus, and system for reducing pipeline stalls due to address translation misses | Pritha Ghoshal, Niket K. Choudhary, Ravi Rajagopalan, Patrick Eibl, Brian Michael Stempel +1 more | 2021-07-13 |
| 11061820 | Optimizing access to page table entries in processor-based devices | — | 2021-07-13 |
| 11016899 | Selectively honoring speculative memory prefetch requests based on bandwidth state of a memory access path component(s) in a processor-based system | Nikhil Narendradev Sharma, Eric F. Robinson, Garrett M. Drapala, Perry Willmann Remaklus, Jr., Joseph Gerald McDonald | 2021-05-25 |
| 10956162 | Operand-based reach explicit dataflow processors, and related methods and computer-readable media | Robert Douglas Clancy, Melinda J. Brown, Yusuf Cagatay Tekmen, Brian Michael Stempel, Michael Scott McIlvaine +3 more | 2021-03-23 |