ER

Eric F. Robinson

IBM: 32 patents #3,111 of 70,183Top 5%
Microsoft: 9 patents #4,890 of 40,388Top 15%
QU Qualcomm: 6 patents #2,896 of 12,104Top 25%
Overall (All Time): #59,889 of 4,157,543Top 2%
47
Patents All Time

Issued Patents All Time

Showing 25 most recent of 47 patents

Patent #TitleCo-InventorsDate
12399829 Dynamic extension of cache coherence snoop filter entry 2025-08-26
12386753 Systems and methods for managing dirty data Kevin N. Magill, Jason Panavich, Michael B. Mitchell, Michael P. Wilson 2025-08-12
12339777 Dynamic extension and de-allocation of cache coherence snoop filter entry 2025-06-24
11550723 Method, apparatus, and system for memory bandwidth aware data prefetching Niket K. Choudhary, David Scott Ray, Thomas Philip Speier, Harold W. Cain, III, Nikhil Narendradev Sharma +3 more 2023-01-10
11372757 Tracking repeated reads to guide dynamic selection of cache coherence protocols in processor-based devices Kevin N. Magill, Derek T. Bachand, Jason Panavich, Michael B. Mitchell, Michael P. Wilson 2022-06-28
11354239 Maintaining domain coherence states including domain state no-owned (DSN) in processor-based devices Kevin N. Magill, Jason Panavich, Derek T. Bachand, Michael B. Mitchell, Michael P. Wilson 2022-06-07
11226910 Ticket based request flow control Joseph Gerald McDonald, Garrett M. Drapala, Thomas Philip Speier, Kevin N. Magill, Richard Gerard Hofmann 2022-01-18
11138114 Providing dynamic selection of cache coherence protocols in processor-based devices Kevin N. Magill, Derek T. Bachand, Jason Panavich, Michael P. Wilson, Michael B. Mitchell 2021-10-05
11119770 Performing atomic store-and-invalidate operations in processor-based devices Thomas Philip Speier 2021-09-14
11093396 Enabling atomic memory accesses across coherence granule boundaries in processor-based devices Derek T. Bachand, Jason Panavich, Kevin N. Magill, Michael B. Mitchell, Michael P. Wilson 2021-08-17
11016899 Selectively honoring speculative memory prefetch requests based on bandwidth state of a memory access path component(s) in a processor-based system Nikhil Narendradev Sharma, Garrett M. Drapala, Perry Willmann Remaklus, Jr., Joseph Gerald McDonald, Thomas Philip Speier 2021-05-25
10896135 Facilitating page table entry (PTE) maintenance in processor-based devices Jason Panavich, Thomas Philip Speier 2021-01-19
9934149 Prefetch mechanism for servicing demand miss Khary J. Alexander 2018-04-03
9817760 Self-healing coarse-grained snoop filter Khary J. Alexander, Zeid H. Samoail, Benjamin Charles Michelson 2017-11-14
9645931 Filtering snoop traffic in a multiprocessor computing system Jason A. Cox, M V V Anil Krishna, Brian M. Rogers 2017-05-09
9323675 Filtering snoop traffic in a multiprocessor computing system Jason A. Cox, M V V Anil Krishna, Brian M. Rogers 2016-04-26
9292442 Methods and apparatus for improving performance of semaphore management sequences across a coherent bus Thomas Philip Speier, Jaya Prakash Subramaniam Ganasan, Thomas Andrew Sartorius, James Norris Dieffenderfer 2016-03-22
9170962 Dynamic designation of retirement order in out-of-order store queue 2015-10-27
8938588 Ensuring forward progress of token-required cache operations in a shared cache Jason A. Cox, Mark J. Wolski 2015-01-20
8930680 Sync-ID for multiple concurrent sync dependencies in an out-of-order store queue 2015-01-06
8850095 Livelock prevention mechanism in a ring shaped interconnect utilizing round robin sampling Amit Golander, Omer Heymann, Nadav Levison 2014-09-30
8707449 Acquiring access to a token controlled system resource Jason A. Cox, Kevin Lin, Mark J. Wolski 2014-04-22
8671247 Transfer of bus-based operations to demand-side machines Jason A. Cox, Kevin Lin, Mark J. Wolski 2014-03-11
8656106 Managing unforced injections of cache lines into a cache utilizing predetermined address ranges Jason A. Cox, Praveen Karandikar, Mark J. Wolski 2014-02-18
8639889 Address-based hazard resolution for managing read/write operations in a memory cache Jason A. Cox, Robert J. Dorsey, Kevin Lin 2014-01-28