| 12386753 |
Systems and methods for managing dirty data |
Kevin N. Magill, Eric F. Robinson, Jason Panavich, Michael P. Wilson |
2025-08-12 |
| 11372757 |
Tracking repeated reads to guide dynamic selection of cache coherence protocols in processor-based devices |
Kevin N. Magill, Eric F. Robinson, Derek T. Bachand, Jason Panavich, Michael P. Wilson |
2022-06-28 |
| 11354239 |
Maintaining domain coherence states including domain state no-owned (DSN) in processor-based devices |
Eric F. Robinson, Kevin N. Magill, Jason Panavich, Derek T. Bachand, Michael P. Wilson |
2022-06-07 |
| 11138114 |
Providing dynamic selection of cache coherence protocols in processor-based devices |
Kevin N. Magill, Eric F. Robinson, Derek T. Bachand, Jason Panavich, Michael P. Wilson |
2021-10-05 |
| 11093396 |
Enabling atomic memory accesses across coherence granule boundaries in processor-based devices |
Eric F. Robinson, Derek T. Bachand, Jason Panavich, Kevin N. Magill, Michael P. Wilson |
2021-08-17 |
| 9201801 |
Computing device with asynchronous auxiliary execution unit |
Bechara F. Boury, Paul M. Steinmetz, Kenichi Tsuchiya |
2015-12-01 |
| 8301992 |
System and apparatus for error-correcting register files |
Anthony J. Bybell, Jason M. Sullivan |
2012-10-30 |
| 7752396 |
Promoting a line from shared to exclusive in a cache |
James Norris Dieffenderfer, Praveen Karandikar, Thomas Philip Speier, Paul M. Steinmetz |
2010-07-06 |
| 7672188 |
System for blocking multiple memory read port activation |
Anthony Correale, Jr., Matthew W. Baker, Benjamin J. Bowers, Nishith Rohatgi |
2010-03-02 |
| 7523265 |
Systems and arrangements for promoting a line to exclusive in a fill buffer of a cache |
James Norris Dieffenderfer, Praveen Karandikar, Thomas Philip Speier, Paul M. Steinmetz |
2009-04-21 |
| 7319578 |
Digital power monitor and adaptive self-tuning power management |
James Norris Dieffenderfer, Praveen Karandikar, Thomas Philip Speier, Paul M. Steinmetz |
2008-01-15 |