Issued Patents All Time
Showing 25 most recent of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12039337 | Processor with multiple fetch and decode pipelines | Robert B. Cohen, Tzu-Wei Lin, Bill Kai Chiu Kwan, Frank C. Galloway | 2024-07-16 |
| 11907126 | Processor with multiple op cache pipelines | Robert B. Cohen, Tzu-Wei Lin, Sudherssen Kalaiselvan, James A. Mossman | 2024-02-20 |
| 10956340 | Hardware-based pre-page walk virtual address transformation independent of page size utilizing bit shifting based on page size | Bradly G. Frey, Michael K. Gschwind | 2021-03-23 |
| 10216642 | Hardware-based pre-page walk virtual address transformation where the virtual address is shifted by current page size and a minimum page size | Bradly G. Frey, Michael K. Gschwind | 2019-02-26 |
| 10146698 | Method and apparatus for power reduction in a multi-threaded mode | — | 2018-12-04 |
| 10037283 | Updating least-recently-used data for greater persistence of higher generality cache entries | John M. King | 2018-07-31 |
| 9864700 | Method and apparatus for power reduction in a multi-threaded mode | — | 2018-01-09 |
| 9811472 | Radix table translation of memory | Michael K. Gschwind | 2017-11-07 |
| 9785569 | Radix table translation of memory | Michael K. Gschwind | 2017-10-10 |
| 9753860 | Page table entry consolidation | Michael K. Gschwind | 2017-09-05 |
| 9740628 | Page table entry consolidation | Michael K. Gschwind | 2017-08-22 |
| 9734083 | Separate memory address translations for instruction fetches and data accesses | Michael K. Gschwind | 2017-08-15 |
| 9734084 | Separate memory address translations for instruction fetches and data accesses | Michael K. Gschwind | 2017-08-15 |
| 9600419 | Selectable address translation mechanisms | Bradly G. Frey, Michael K. Gschwind | 2017-03-21 |
| 9348763 | Asymmetric co-existent address translation structure formats | David D. Dukro, Bradly G. Frey, Michael K. Gschwind | 2016-05-24 |
| 9330023 | Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces | Bradly G. Frey, Michael K. Gschwind, Benjamin Herrenschmidt, Paul Mackerras | 2016-05-03 |
| 9323692 | Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer | Bradly G. Frey, Michael K. Gschwind, Benjamin Herrenschmidt, Paul Mackerras | 2016-04-26 |
| 9317443 | Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces | Bradly G. Frey, Michael K. Gschwind, Benjamin Herrenschmidt, Paul Mackerras | 2016-04-19 |
| 9311249 | Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer | Bradly G. Frey, Michael K. Gschwind, Benjamin Herrenschmidt, Paul Mackerras | 2016-04-12 |
| 9280488 | Asymmetric co-existent address translation structure formats | David D. Dukro, Bradly G. Frey, Michael K. Gschwind | 2016-03-08 |
| 9256550 | Hybrid address translation | Michael K. Gschwind | 2016-02-09 |
| 9251092 | Hybrid address translation | Michael K. Gschwind | 2016-02-02 |
| 9092359 | Identification and consolidation of page table entries | Michael K. Gschwind | 2015-07-28 |
| 9086988 | Identification and consolidation of page table entries | Michael K. Gschwind | 2015-07-21 |
| 8782380 | Fine-grained privilege escalation | Anup Wadia | 2014-07-15 |