Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11755362 | Techniques for handling escalation of interrupts in a data processing system | Florian A. Auernhammer | 2023-09-12 |
| 11461474 | Process-based virtualization system for executing a secure application process | Jentje Leenstra, Paul Mackerras, Bradly G. Frey, John Martin Ludden, Guerney D. H. Hunt +1 more | 2022-10-04 |
| 11226902 | Translation load instruction with access protection | Derek E. Williams, Cathy May, Bradly G. Frey | 2022-01-18 |
| 11221957 | Promotion of ERAT cache entries | Bartholomew Blaner, Jay G. Heaslip, Robert D. Herzl, Jody B. Joyner, Jon K. Kriegel +1 more | 2022-01-11 |
| 10817434 | Interruptible translation entry invalidation in a multithreaded data processing system | Derek E. Williams, Cathy May, Bradly G. Frey | 2020-10-27 |
| 10776281 | Snoop invalidate filter for distributed memory management unit to reduce snoop invalidate latency | Jake Truelove, Ronald Nick Kalla, Jody B. Joyner, David A. Larson Stanton | 2020-09-15 |
| 10387686 | Hardware based isolation for secure execution of virtual machines | Richard H. Boivie, Bradly G. Frey, William E. Hall, Guerney D. H. Hunt, Jentje Leenstra +3 more | 2019-08-20 |
| 10255194 | Configurable I/O address translation data structure | Richard Louis Arndt, Eric N. Lais, Steven M. Thurber | 2019-04-09 |
| 10241923 | Configurable I/O address translation data structure | Richard Louis Arndt, Eric N. Lais, Steven M. Thurber | 2019-03-26 |
| 9626187 | Transactional memory system supporting unbroken suspended execution | Harold W. Cain, III, Bradly G. Frey, Hung Q. Le, Cathy May, Maged M. Michael +4 more | 2017-04-18 |
| 9575728 | Random number generation security | Bartholomew Blaner, David A. Larson Stanton, Derek E. Williams | 2017-02-21 |
| 9417846 | Techniques for improving random number generation security | Bartholomew Blaner, David A. Larson Stanton, Derek E. Williams | 2016-08-16 |
| 9330023 | Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces | Anthony J. Bybell, Bradly G. Frey, Michael K. Gschwind, Paul Mackerras | 2016-05-03 |
| 9323692 | Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer | Anthony J. Bybell, Bradly G. Frey, Michael K. Gschwind, Paul Mackerras | 2016-04-26 |
| 9317443 | Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces | Anthony J. Bybell, Bradly G. Frey, Michael K. Gschwind, Paul Mackerras | 2016-04-19 |
| 9311249 | Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer | Anthony J. Bybell, Bradly G. Frey, Michael K. Gschwind, Paul Mackerras | 2016-04-12 |
| 9251088 | Mechanisms for eliminating a race condition between a hypervisor-performed emulation process requiring a translation operation and a concurrent translation table entry invalidation | Bradly G. Frey, Michael K. Gschwind | 2016-02-02 |
| 8688953 | Method and apparatus for managing software controlled cache of translating the physical memory access of a virtual machine between different levels of translation entities | Hubertus Franke, Jon K. Kriegel, Andrew M. Theurer, James Xenidis | 2014-04-01 |
| 8364933 | Software assisted translation lookaside buffer search mechanism | Jason Michael Hopp, Kenichi Tsuchiya, Maciej Piotr Tyrlik | 2013-01-29 |
| 8296547 | Loading entries into a TLB in hardware via indirect TLB entries | Timothy H. Heil, Jon K. Kriegel, Paul Mackerras, Andrew Henry Wottreng | 2012-10-23 |
| 8275971 | Method and apparatus for managing software controlled cache of translating the physical memory access of a virtual machine between different levels of translation entities | Hubertus Franke, Jon K. Kriegel, Andrew M. Theurer, James Xenidis | 2012-09-25 |