Issued Patents All Time
Showing 25 most recent of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12223098 | Systems and methods for dynamic control of a secure mode of operation in a processor | Debapriya Chatterjee, Christian Zoellin, Brian W. Thompto | 2025-02-11 |
| 11797713 | Systems and methods for dynamic control of a secure mode of operation in a processor | Debapriya Chatterjee, Christian Zoellin, Brian W. Thompto | 2023-10-24 |
| 11461474 | Process-based virtualization system for executing a secure application process | Jentje Leenstra, Paul Mackerras, Benjamin Herrenschmidt, John Martin Ludden, Guerney D. H. Hunt +1 more | 2022-10-04 |
| 11226902 | Translation load instruction with access protection | Derek E. Williams, Benjamin Herrenschmidt, Cathy May | 2022-01-18 |
| 11119932 | Operation of a multi-slice processor implementing adaptive prefetch control | George W. Rohrbaugh, III, Brian W. Thompto | 2021-09-14 |
| 10956340 | Hardware-based pre-page walk virtual address transformation independent of page size utilizing bit shifting based on page size | Anthony J. Bybell, Michael K. Gschwind | 2021-03-23 |
| 10817434 | Interruptible translation entry invalidation in a multithreaded data processing system | Derek E. Williams, Benjamin Herrenschmidt, Cathy May | 2020-10-27 |
| 10613792 | Efficient enforcement of barriers with respect to memory move sequences | Guy L. Guthrie, Cathy May, William J. Starke, Derek E. Williams | 2020-04-07 |
| 10387686 | Hardware based isolation for secure execution of virtual machines | Richard H. Boivie, William E. Hall, Benjamin Herrenschmidt, Guerney D. H. Hunt, Jentje Leenstra +3 more | 2019-08-20 |
| 10331566 | Operation of a multi-slice processor implementing adaptive prefetch control | George W. Rohrbaugh, III, Brian W. Thompto | 2019-06-25 |
| 10216642 | Hardware-based pre-page walk virtual address transformation where the virtual address is shifted by current page size and a minimum page size | Anthony J. Bybell, Michael K. Gschwind | 2019-02-26 |
| 10152322 | Memory move instruction sequence including a stream of copy-type and paste-type instructions | Sanjeev Ghai, Guy L. Guthrie, Cathy May, William J. Starke, Derek E. Williams | 2018-12-11 |
| 10067713 | Efficient enforcement of barriers with respect to memory move sequences | Guy L. Guthrie, Cathy May, William J. Starke, Derek E. Williams | 2018-09-04 |
| 9785557 | Translation entry invalidation in a multithreaded data processing system | Guy L. Guthrie, Cathy May, Derek E. Williams | 2017-10-10 |
| 9772945 | Translation entry invalidation in a multithreaded data processing system | Guy L. Guthrie, Cathy May, Derek E. Williams | 2017-09-26 |
| 9747212 | Virtual unifed instruction and data caches including storing program instructions and memory address in CAM indicated by store instruction containing bit directly indicating self modifying code | Wen-Tzer T. Chen, Robert H. Bell, Jr. | 2017-08-29 |
| 9626187 | Transactional memory system supporting unbroken suspended execution | Harold W. Cain, III, Benjamin Herrenschmidt, Hung Q. Le, Cathy May, Maged M. Michael +4 more | 2017-04-18 |
| 9626256 | Determining failure context in hardware transactional memories | Harold W. Cain, III, Hung Q. Le, Cathy May | 2017-04-18 |
| 9619345 | Apparatus for determining failure context in hardware transactional memories | Harold W. Cain, III, Hung Q. Le, Cathy May | 2017-04-11 |
| 9600419 | Selectable address translation mechanisms | Anthony J. Bybell, Michael K. Gschwind | 2017-03-21 |
| 9575825 | Push instruction for pushing a message payload from a sending thread to a receiving thread | Lakshminarayana B. Arimilli, Bernard C. Drerup, Guy L. Guthrie, John D. Irish, William J. Starke +1 more | 2017-02-21 |
| 9569293 | Push instruction for pushing a message payload from a sending thread to a receiving thread | Lakshminarayana B. Arimilli, Bernard C. Drerup, Guy L. Guthrie, John D. Irish, William J. Starke +1 more | 2017-02-14 |
| 9430166 | Interaction of transactional storage accesses with other atomic semantics | Guy L. Guthrie, Cathy May, Derek E. Williams | 2016-08-30 |
| 9396115 | Rewind only transactions in a data processing system supporting transactional storage accesses | Robert J. Blainey, Guy L. Guthrie, Cathy May, Derek E. Williams | 2016-07-19 |
| 9367264 | Transaction check instruction for memory transactions | Guy L. Guthrie, Cathy May, Derek E. Williams | 2016-06-14 |