| 12411996 |
Hardware-based implementation of secure hash algorithms |
Manoj Kumar, Silvia M. Mueller, Niels Fricke, Kattamuri Ekanadham, Maarten J. Boersma +1 more |
2025-09-09 |
| 12288064 |
Hardware-based message block padding for hash algorithms |
Manoj Kumar, Silvia M. Mueller, Niels Fricke, Martijn Diede Berkers |
2025-04-29 |
| 12223098 |
Systems and methods for dynamic control of a secure mode of operation in a processor |
Christian Zoellin, Bradly G. Frey, Brian W. Thompto |
2025-02-11 |
| 12164921 |
Comparing hash values computed at function entry and exit for increased security |
Jose E. Moreira, Arnold Flores, Kattamuri Ekanadham |
2024-12-10 |
| 12045471 |
Secure memory isolation for secure endpoints |
Guerney D. H. Hunt, Eric N. Lais |
2024-07-23 |
| 12008149 |
Method and system for on demand control of hardware support for software pointer authentification in a computing system |
Brian W. Thompto, Jose E. Moreira |
2024-06-11 |
| 11853195 |
Methods and systems to discover special outcomes in an instruction set architecture via formal methods |
Gregory A. Kemp, Bryant Cockcroft, Bradley Donald Bingham |
2023-12-26 |
| 11797713 |
Systems and methods for dynamic control of a secure mode of operation in a processor |
Christian Zoellin, Bradly G. Frey, Brian W. Thompto |
2023-10-24 |
| 11556365 |
Obscuring information in virtualization environment |
Bryant Cockcroft, John A. Schumann, Karen Yokum |
2023-01-17 |
| 11475191 |
Generating and adding additional control information to logic under test to facilitate debugging and comprehension of a simulation |
Paul Umbarger, Karen Yokum, John A. Schumann, Bryant Cockcroft, Kevin Barnett |
2022-10-18 |
| 11436013 |
Method and system for detection of thread stall |
Omesh Bajaj, Kevin Barnett, Bryant Cockcroft, Jamory Hawkins, Lance G. Hehenberger +7 more |
2022-09-06 |
| 11301392 |
Address translation cache invalidation in a microprocessor |
Bryant Cockcroft, Larry Scott Leitner, John A. Schumann, Karen Yokum |
2022-04-12 |
| 11243864 |
Identifying translation errors |
Bryant Cockcroft, John A. Schumann, Larry Scott Leitner, Kevin Barnett, Karen Yokum |
2022-02-08 |
| 11157285 |
Dynamic modification of instructions that do not modify the architectural state of a processor |
Bryant Cockcroft, John A. Schumann, Karen Yokum, Vivek Britto |
2021-10-26 |
| 11080122 |
Software-invisible interrupt for a microprocessor |
Larry Scott Leitner, John A. Schumann, Wallace Sharp, Bryant Cockcroft |
2021-08-03 |
| 10942853 |
System and method including broadcasting an address translation invalidation instruction with a return marker to indentify the location of data in a computing system having mutiple processors |
John A. Schumann, Bryant Cockcroft, Lawrence Leitner, Karen Yokum |
2021-03-09 |
| 10915456 |
Address translation cache invalidation in a microprocessor |
Bryant Cockcroft, Larry Scott Leitner, John A. Schumann, Karen Yokum |
2021-02-09 |
| 10896273 |
Precise verification of a logic problem on a simulation accelerator |
John A. Schumann, Bryant Cockcroft, Kevin Barnett, Piriya K. Hall, Paul Umbarger +1 more |
2021-01-19 |
| 10705843 |
Method and system for detection of thread stall |
Omesh Bajaj, Kevin Barnett, Bryant Cockcroft, Jamory Hawkins, Lance G. Hehenberger +7 more |
2020-07-07 |
| 10539614 |
Circuit design verification in a hardware accelerated simulation environment using breakpoints |
Rahul Batra, John C. Goss, Christopher R. Jones, Christopher M. Riedl, John A. Schumann +1 more |
2020-01-21 |
| 10228422 |
Driving pervasive commands using breakpoints in a hardware-accelerated simulation environment |
Shakti Kapoor, John A. Schumann |
2019-03-12 |
| 9939487 |
Circuit design verification in a hardware accelerated simulation environment using breakpoints |
Rahul Batra, John C. Goss, Christopher R. Jones, Christopher M. Riedl, John A. Schumann +1 more |
2018-04-10 |
| 9747396 |
Driving pervasive commands using breakpoints in a hardware-accelerated simulation environment |
Shakti Kapoor, John A. Schumann |
2017-08-29 |
| 8738349 |
Gate-level logic simulator using multiple processor architectures |
Valeria Bertacco, Andrew DeOrio |
2014-05-27 |
| 8601418 |
Instruction-by-instruction checking on acceleration platforms |
Anatoly Koyfman, Ronny Morad, Avi Ziv |
2013-12-03 |
