Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411996 | Hardware-based implementation of secure hash algorithms | Manoj Kumar, Silvia M. Mueller, Debapriya Chatterjee, Kattamuri Ekanadham, Maarten J. Boersma +1 more | 2025-09-09 |
| 12288064 | Hardware-based message block padding for hash algorithms | Manoj Kumar, Silvia M. Mueller, Debapriya Chatterjee, Martijn Diede Berkers | 2025-04-29 |
| 11561798 | On-the-fly adjustment of issue-write back latency to avoid write back collisions using a result buffer | Brian D. Barrick, Maarten J. Boersma, Dung Q. Nguyen, Brian W. Thompto, Andreas Wagner | 2023-01-24 |
| 11392386 | Program counter (PC)-relative load and store addressing for fused instructions | Nicholas R. Orzol, Christian Zoellin, Brian W. Thompto, Dung Q. Nguyen, Sheldon B. Levenstein +2 more | 2022-07-19 |
| 11182167 | Method to determine the oldest instruction in an instruction queue of a processor with multiple instruction threads | Arni Ingimundarson, Maarten J. Boersma | 2021-11-23 |
| 11163571 | Fusion to enhance early address generation of load instructions in a microprocessor | Brian D. Barrick, Sundeep Chadha, Sheldon B. Levenstein, Phillip G. Williams, Dung Q. Nguyen +2 more | 2021-11-02 |
| 11157276 | Thread-based organization of slice target register file entry in a microprocessor to permit writing scalar or vector data to portions of a single register file entry | Steven J. Battle, Maarten J. Boersma, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto | 2021-10-26 |
| 11093246 | Banked slice-target register file for wide dataflow execution in a microprocessor | Maarten J. Boersma, Michael K. Kroener, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto | 2021-08-17 |
| 10996953 | Low latency execution of floating-point record form instructions | Brian J. D. Barrick, Maarten J. Boersma, Michael J. Genden | 2021-05-04 |
| 10831496 | Method to execute successive dependent instructions from an instruction stream in a processor | Maarten J. Boersma, Michael K. Kroener, Razvan Peter Figuli, Nandor Szirmak, Dung Q. Nguyen | 2020-11-10 |
| 10768897 | Arithmetic logic unit for single-cycle fusion operations | Maarten J. Boersma | 2020-09-08 |
| 10678547 | Low latency execution of floating-point record form instructions | Brian J. D. Barrick, Maarten J. Boersma, Michael J. Genden | 2020-06-09 |
| 10592246 | Low latency execution of floating-point record form instructions | Brian J. D. Barrick, Maarten J. Boersma, Michael J. Genden | 2020-03-17 |
| 10545727 | Arithmetic logic unit for single-cycle fusion operations | Maarten J. Boersma | 2020-01-28 |
| 10360036 | Cracked execution of move-to-FPSCR instructions | Brian J. D. Barrick, Maarten J. Boersma, Michael J. Genden | 2019-07-23 |
| 9928128 | In-pipe error scrubbing within a processor core | Brian D. Barrick, James Wilson Bishop, Marcy E. Byers, Sundeep Chadha, Dung Q. Nguyen +1 more | 2018-03-27 |
| 9727687 | Method for calculating an effect on timing of moving a pin from an edge to an inboard position in processing large block synthesis (LBS) | Lukas Daellenbach, Michael H. Wood | 2017-08-08 |
| 9536030 | Optimization of integrated circuit physical design | Karsten Muuss, Peter Verwegen, Christoph Wandel | 2017-01-03 |
| 9418198 | Method for calculating an effect on timing of moving a pin from an edge to an inboard position in processing large block synthesis (LBS) | Lukas Daellenbach, Michael H. Wood | 2016-08-16 |
| 8522187 | Method and data processing system to optimize performance of an electric circuit design, data processing program and computer program product | Bernd Kemmler, Juergen Koehl, Karsten Muuss, Matthias Ringe | 2013-08-27 |