Issued Patents All Time
Showing 25 most recent of 88 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11995445 | Assignment of microprocessor register tags at issue time | Steven J. Battle, Jentje Leenstra, Dung Q. Nguyen, Brian W. Thompto | 2024-05-28 |
| 11941398 | Fast mapper restore for flush in processor | Steven J. Battle, Dung Q. Nguyen, Susan E. Eisen, Cliff Kucharski, Salma Ayub | 2024-03-26 |
| 11886883 | Dependency skipping in a load-compare-jump sequence of instructions by incorporating compare functionality into the jump instruction and auto-finishing the compare instruction | Nicholas R. Orzol, Mehul Patel, Dung Q. Nguyen, Richard J. Eickemeyer, John B. Griswell, Jr. +3 more | 2024-01-30 |
| 11868773 | Inferring future value for speculative branch resolution in a microprocessor | Steven J. Battle, Dung Q. Nguyen, Richard J. Eickemeyer, John B. Griswell, Jr., Balaram Sinharoy +2 more | 2024-01-09 |
| 11709676 | Inferring future value for speculative branch resolution | Steven J. Battle, Dung Q. Nguyen, Richard J. Eickemeyer, John B. Griswell, Jr., Balaram Sinharoy +2 more | 2023-07-25 |
| 11663013 | Dependency skipping execution | Nicholas R. Orzol, Mehul Patel, Dung Q. Nguyen, Richard J. Eickemeyer, John B. Griswell, Jr. +3 more | 2023-05-30 |
| 11561798 | On-the-fly adjustment of issue-write back latency to avoid write back collisions using a result buffer | Maarten J. Boersma, Niels Fricke, Dung Q. Nguyen, Brian W. Thompto, Andreas Wagner | 2023-01-24 |
| 11537402 | Execution elision of intermediate instruction by processor | Bryan Lloyd, Dung Q. Nguyen, Brian W. Thompto, Edmund J. Gieske, John B. Griswell, Jr. | 2022-12-27 |
| 11531548 | Fast perfect issue of dependent instructions in a distributed issue queue system | Dung Q. Nguyen, Brian W. Thompto, Tu-An T. Nguyen, Salma Ayub | 2022-12-20 |
| 11500642 | Assignment of microprocessor register tags at issue time | Steven J. Battle, Jentje Leenstra, Dung Q. Nguyen, Brian W. Thompto | 2022-11-15 |
| 11403109 | Steering a history buffer entry to a specific recovery port during speculative flush recovery lookup in a processor | Steven J. Battle, Khandker N. Adeeb, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard +2 more | 2022-08-02 |
| 11392386 | Program counter (PC)-relative load and store addressing for fused instructions | Nicholas R. Orzol, Christian Zoellin, Brian W. Thompto, Dung Q. Nguyen, Niels Fricke +2 more | 2022-07-19 |
| 11360779 | Logical register recovery within a processor | Steven J. Battle, Salma Ayub, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard +2 more | 2022-06-14 |
| 11360775 | Slice-based allocation history buffer | Gregory W. Alexander, Dung Q. Nguyen | 2022-06-14 |
| 11327757 | Processor providing intelligent management of values buffered in overlaid architected and non-architected register files | Steven J. Battle, Kurt A. Feiste, Susan E. Eisen, Dung Q. Nguyen, Christian Zoellin +4 more | 2022-05-10 |
| 11249757 | Handling and fusing load instructions in a processor | Bryan Lloyd, Brian W. Thompto, Dung Q. Nguyen, Sheldon B. Levenstein, Christian Zoellin | 2022-02-15 |
| 11194578 | Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor | Steven J. Battle, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Cliff Kucharski +2 more | 2021-12-07 |
| 11188332 | System and handling of register data in processors | Steven J. Battle, Salma Ayub, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard +2 more | 2021-11-30 |
| 11182164 | Pairing issue queues for complex instructions and instruction fusion | John B. Griswell, Jr., Dung Q. Nguyen, Brian W. Thompto | 2021-11-23 |
| 11163571 | Fusion to enhance early address generation of load instructions in a microprocessor | Sundeep Chadha, Sheldon B. Levenstein, Phillip G. Williams, Niels Fricke, Dung Q. Nguyen +2 more | 2021-11-02 |
| 11144364 | Supporting speculative microprocessor instruction execution | Steven J. Battle, Brandon Goddard, Dung Q. Nguyen, Joshua W. Bowman, Susan E. Eisen +2 more | 2021-10-12 |
| 11138050 | Operation of a multi-slice processor implementing a hardware level transfer of an execution thread | James Wilson Bishop, Marcy E. Byers, Sundeep Chadha, Cliff Kucharski, Dung Q. Nguyen +2 more | 2021-10-05 |
| 11119772 | Check pointing of accumulator register results in a microprocessor | Steven J. Battle, Susan E. Eisen, Andreas Wagner, Dung Q. Nguyen, Brian W. Thompto +2 more | 2021-09-14 |
| 11093282 | Register file write using pointers | Steven J. Battle, Joshua W. Bowman, Cliff Kucharski, Hung Q. Le, Dung Q. Nguyen +1 more | 2021-08-17 |
| 11068267 | High bandwidth logical register flush recovery | Steven J. Battle, Brandon Goddard, Dung Q. Nguyen, Joshua W. Bowman, Susan E. Eisen +2 more | 2021-07-20 |