Issued Patents All Time
Showing 25 most recent of 64 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411688 | Gather buffer management for unaligned and gather load operations | Kimberly M. Fernsler, David A. Hrusecky, David Campbell | 2025-09-09 |
| 11775337 | Prioritization of threads in a simultaneous multithreading processor core | Guy L. Guthrie, Susan E. Eisen, Dhivya Jeganathan, Luke Murray | 2023-10-03 |
| 11755324 | Gather buffer management for unaligned and gather load operations | Kimberly M. Fernsler, David A. Hrusecky, David Campbell | 2023-09-12 |
| 11748104 | Microprocessor that fuses load and compare instructions | David A. Hrusecky, Sundeep Chadha, Dung Q. Nguyen, Christian Zoellin, Brian W. Thompto +2 more | 2023-09-05 |
| 11687337 | Processor overriding of a false load-hit-store detection | Brian Chen, Kimberly M. Fernsler | 2023-06-27 |
| 11650926 | Virtual cache synonym detection using alias tags | David Campbell | 2023-05-16 |
| 11645208 | Translation bandwidth optimized prefetching strategy through multiple translation lookaside buffers | David Campbell, George W. Rohrbaugh, III, Vivek Britto, Mohit Karve | 2023-05-09 |
| 11537519 | Marking in-flight requests affected by translation entry invalidation in a data processing system | Derek E. Williams, Guy L. Guthrie, Hugh Shen, David Campbell, Samuel David Kirchhoff +1 more | 2022-12-27 |
| 11537402 | Execution elision of intermediate instruction by processor | Brian D. Barrick, Dung Q. Nguyen, Brian W. Thompto, Edmund J. Gieske, John B. Griswell, Jr. | 2022-12-27 |
| 11520585 | Prefetch store preallocation in an effective address-based cache directory | Brian W. Thompto, George W. Rohrbaugh, III, Mohit Karve, Vivek Britto | 2022-12-06 |
| 11520704 | Writing store data of multiple store operations into a cache line in a single cycle | Robert A. Cordes | 2022-12-06 |
| 11500774 | Virtual cache tag renaming for synonym handling | David Campbell | 2022-11-15 |
| 11379241 | Handling oversize store to load forwarding in a processor | Brian Chen, Kimberly M. Fernsler, Robert A. Cordes, David A. Hrusecky | 2022-07-05 |
| 11321088 | Tracking load and store instructions and addresses in an out-of-order processor | Samuel David Kirchhoff, Brian Chen, Kimberly M. Fernsler, David A. Hrusecky | 2022-05-03 |
| 11314510 | Tracking load and store instructions and addresses in an out-of-order processor | Samuel David Kirchhoff, Brian Chen, Kimberly M. Fernsler, David A. Hrusecky | 2022-04-26 |
| 11263151 | Dynamic translation lookaside buffer (TLB) invalidation using virtually tagged cache for load/store operations | David Campbell, David A. Hrusecky, Kimberly M. Fernsler, Jeffrey A. Stuecheli, Guy L. Guthrie +4 more | 2022-03-01 |
| 11249757 | Handling and fusing load instructions in a processor | Brian W. Thompto, Dung Q. Nguyen, Sheldon B. Levenstein, Brian D. Barrick, Christian Zoellin | 2022-02-15 |
| 11243773 | Area and power efficient mechanism to wakeup store-dependent loads according to store drain merges | David Campbell, Brian Chen, Robert A. Cordes | 2022-02-08 |
| 11175924 | Load-store unit with partitioned reorder queues with single cam port | Christopher Gonzalez, Balaram Sinharoy | 2021-11-16 |
| 11175925 | Load-store unit with partitioned reorder queues with single cam port | Christopher Gonzalez, Balaram Sinharoy | 2021-11-16 |
| 11119945 | Context tracking for multiple virtualization layers in a virtually tagged cache | Jake Truelove, David Campbell | 2021-09-14 |
| 11086787 | Virtual cache synonym detection using alias tags | David Campbell | 2021-08-10 |
| 11061810 | Virtual cache mechanism for program break point register exception handling | David Campbell, Dwain A. Hicks, David A. Hrusecky | 2021-07-13 |
| 10977175 | Virtual cache tag renaming for synonym handling | David Campbell | 2021-04-13 |
| 10977047 | Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses | Balaram Sinharoy, Shih-Hsiung S. Tung | 2021-04-13 |