Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12394468 | Row hammer mitigation using hierarchical detectors | Cagdas Dirik, Robert M. Walker | 2025-08-19 |
| 12315553 | Selectable row hammer mitigation | Sujeet Ayyapureddi, Niccolò Izzo | 2025-05-27 |
| 12248567 | Row hammer interrupts to the operating system | Sujeet Ayyapureddi, Tamara Schmitz, Nicolo Izzo, Markus H. Geiger | 2025-03-11 |
| 12230311 | Aliased row hammer detector | Cagdas Dirik, Robert M. Walker, Sujeet Ayyapureddi, Niccolò Izzo, Markus H. Geiger +4 more | 2025-02-18 |
| 12217824 | Finite time counting period counting of infinite data streams | Amitava Majumdar, Cagdas Dirik, Sujeet Ayyapureddi, Yang Lu, Ameen D. Akel +4 more | 2025-02-04 |
| 12182413 | Area-optimized row hammer mitigation | Sujeet Ayyapureddi, Yang Lu, Cagdas Dirik, Ameen D. Akel, Elliott C. Cooper-Balis +3 more | 2024-12-31 |
| 12119043 | Practical and efficient row hammer error detection | Sujeet Ayyapureddi, Yang Lu, Amitava Majumdar | 2024-10-15 |
| 12073090 | Cache-assisted row hammer mitigation | Cagdas Dirik | 2024-08-27 |
| 12067270 | Memory device security and row hammer mitigation | Yang Lu, Sujeet Ayyapureddi, Cagdas Dirik, Ameen D. Akel, Elliott C. Cooper-Balis +3 more | 2024-08-20 |
| 11994990 | Memory media row activation-biased caching | Cagdas Dirik | 2024-05-28 |
| 11537402 | Execution elision of intermediate instruction by processor | Brian D. Barrick, Bryan Lloyd, Dung Q. Nguyen, Brian W. Thompto, John B. Griswell, Jr. | 2022-12-27 |
| 11520588 | Prefetch filter table for storing moderately-confident entries evicted from a history table | Mohit Karve | 2022-12-06 |
| 11481219 | Store prefetches for dependent loads in a processor | Mohit Karve, George W. Rohrbaugh, III | 2022-10-25 |
| 11416257 | Hybrid and aggregrate branch prediction system with a tagged branch orientation predictor for prediction override or pass-through | Naga P. Gorti, Ehsan Fatehi, Nicholas R. Orzol, Christian Zoellin | 2022-08-16 |
| 11194575 | Instruction address based data prediction and prefetching | Mohit Karve, Naga P. Gorti | 2021-12-07 |
| 11182161 | Fractional or partial line usage prediction in a processor | Mohit Karve, Naga P. Gorti | 2021-11-23 |
| 11163683 | Dynamically adjusting prefetch depth | Mohit Karve, Vivek Britto, George W. Rohrbaugh, III | 2021-11-02 |
| 11016900 | Limiting table-of-contents prefetching consequent to symbol table requests | Mohit Karve | 2021-05-25 |
| 10956164 | Gating updates to branch predictors to reduce pollution from infrequently executed branches | Naga P. Gorti | 2021-03-23 |
| 10942743 | Splitting load hit store table for out-of-order processor | Ehsan Fatehi, Richard J. Eickemeyer | 2021-03-09 |
| 10725783 | Splitting load hit store table for out-of-order processor | Ehsan Fatehi, Richard J. Eickemeyer | 2020-07-28 |
| 8984254 | Techniques for utilizing translation lookaside buffer entry numbers to improve processor performance | Thang M. Tran | 2015-03-17 |
| 8677205 | Hierarchical error correction for large memories | Ravindraraj Ramaraju, David F. Greenberg | 2014-03-18 |
| 8458447 | Branch target buffer addressing in a data processor | Thang M. Tran, Michael Brian SCHINZLER | 2013-06-04 |