Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12394468 | Row hammer mitigation using hierarchical detectors | Edmund J. Gieske, Robert M. Walker | 2025-08-19 |
| 12386559 | Access tracking in memory | Robert M. Walker, Elliott C. Cooper-Balis | 2025-08-12 |
| 12230311 | Aliased row hammer detector | Edmund J. Gieske, Robert M. Walker, Sujeet Ayyapureddi, Niccolò Izzo, Markus H. Geiger +4 more | 2025-02-18 |
| 12216586 | Dynamically sized redundant write buffer with sector-based tracking | Robert M. Walker | 2025-02-04 |
| 12217824 | Finite time counting period counting of infinite data streams | Edmund J. Gieske, Amitava Majumdar, Sujeet Ayyapureddi, Yang Lu, Ameen D. Akel +4 more | 2025-02-04 |
| 12182413 | Area-optimized row hammer mitigation | Sujeet Ayyapureddi, Yang Lu, Edmund J. Gieske, Ameen D. Akel, Elliott C. Cooper-Balis +3 more | 2024-12-31 |
| 12073090 | Cache-assisted row hammer mitigation | Edmund J. Gieske | 2024-08-27 |
| 12067270 | Memory device security and row hammer mitigation | Yang Lu, Sujeet Ayyapureddi, Edmund J. Gieske, Ameen D. Akel, Elliott C. Cooper-Balis +3 more | 2024-08-20 |
| 11994990 | Memory media row activation-biased caching | Edmund J. Gieske | 2024-05-28 |
| 11899591 | Dynamically sized redundant write buffer with sector-based tracking | Robert M. Walker | 2024-02-13 |
| 11893279 | Access tracking in memory | Robert M. Walker, Elliott C. Cooper-Balis | 2024-02-06 |
| 11886348 | Interleaved cache prefetching | Laurent Isenegger, Robert M. Walker | 2024-01-30 |
| 11822790 | Cache line data | Robert M. Walker | 2023-11-21 |
| 11599472 | Interleaved cache prefetching | Laurent Isenegger, Robert M. Walker | 2023-03-07 |
| 11550725 | Dynamically sized redundant write buffer with sector-based tracking | Robert M. Walker | 2023-01-10 |
| 11397683 | Low latency cache for non-volatile memory in a hybrid DIMM | Horia Simionescu, Paul Stonelake, Chung Kuang Chin, Narasimhulu Dharanikumar Kotte, Robert M. Walker | 2022-07-26 |
| 11301383 | Managing processing of memory commands in a memory subsystem with a high latency backing store | Patrick A. La Fratta, Laurent Isenegger, Robert M. Walker | 2022-04-12 |
| 11188234 | Cache line data | Robert M. Walker | 2021-11-30 |