Issued Patents All Time
Showing 1–25 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12260110 | Managing trim commands in a memory sub-system | Yueh-Hung Chen, Fangfang Zhu, Chih-Kuo Kao, Jiangli Zhu | 2025-03-25 |
| 12066949 | Address translation based on page identifier and queue identifier | Chung Kuang Chin, Di-Hsien Ngu | 2024-08-20 |
| 11995314 | Memory management | Chung Kuang Chin | 2024-05-28 |
| 11868642 | Managing trim commands in a memory sub-system | Yueh-Hung Chen, Fangfang Zhu, Chih-Kuo Kao, Jiangli Zhu | 2024-01-09 |
| 11803321 | Interruption of program operations at a memory sub-system | Rohitkumar Makhija, Peng-Cheng Chen, Jung Sheng Hoei | 2023-10-31 |
| 11789819 | Seamless recovery of a hardware-based I/O path in a multi-function NVMe SSD | Ramkumar Venkatachalam, Anirban Kundu | 2023-10-17 |
| 11698876 | Quality of service control of logical devices for a memory sub-system | Xiaodong Wang, Venkata Yaswanth Raparti | 2023-07-11 |
| 11561902 | Cache operations in a hybrid dual in-line memory module | Paul Stonelake, Samir Mittal, Robert W. Walker, Anirban Ray, Gurpreet Anand | 2023-01-24 |
| 11531622 | Managing data dependencies for out of order processing in a hybrid DIMM | Chung Kuang Chin, Paul Stonelake, Narasimhulu Dharanikumar Kotte | 2022-12-20 |
| 11513959 | Managing collisions in a non-volatile memory system with a coherency checker | Lyle E. Adams, Yongcai Xu, Mark Ish | 2022-11-29 |
| 11494306 | Managing data dependencies in a transfer pipeline of a hybrid dimm | Chung Kuang Chin, Paul Stonelake, Narasimhulu Dharanikumar Kotte | 2022-11-08 |
| 11442656 | Interruption of program operations at a memory sub-system | Rohitkumar Makhija, Peng-Cheng Chen, Jung Sheng Hoei | 2022-09-13 |
| 11397683 | Low latency cache for non-volatile memory in a hybrid DIMM | Paul Stonelake, Chung Kuang Chin, Narasimhulu Dharanikumar Kotte, Robert M. Walker, Cagdas Dirik | 2022-07-26 |
| 11321257 | Quality of service control of logical devices for a memory sub-system | Xiaodong Wang, Venkata Yaswanth Raparti | 2022-05-03 |
| 11169920 | Cache operations in a hybrid dual in-line memory module | Paul Stonelake, Samir Mittal, Robert M. Walker, Anirban Ray, Gurpreet Anand | 2021-11-09 |
| 10936496 | Managing collisions in a non-volatile memory system with a coherency checker | Lyle E. Adams, Yongcai Xu, Mark Ish | 2021-03-02 |
| 10929056 | Interruption of program operations at a memory sub-system | Rohitkumar Makhija, Peng-Cheng Chen, Jung Sheng Hoei | 2021-02-23 |
| 10649906 | Method and system for hardware accelerated row lock for a write back volume | Timothy E. Hoglund, Sridhar Rao Veerla, Panthini Pandit, Gowrisankar Radhakrishnan | 2020-05-12 |
| 10528438 | Method and system for handling bad blocks in a hardware accelerated caching solution | Gowrisankar Radhakrishnan, Timothy E. Hoglund, Sridhar Rao Veerla, Panthini Pandit | 2020-01-07 |
| 10423357 | Devices and methods for managing memory buffers | Allen Kelton, Timothy E. Hoglund, Sumanesh Samanta | 2019-09-24 |
| 10394673 | Method and system for hardware accelerated copyback | Timothy E. Hoglund, Sridhar Rao Veerla, Panthini Pandit, Gowrisankar Radhakrishnan | 2019-08-27 |
| 10282301 | Method and system for hardware accelerated read-ahead caching | Timothy E. Hoglund, Sridhar Rao Veerla, Panthini Pandit, Gowrisankar Radhakrishnan | 2019-05-07 |
| 10282116 | Method and system for hardware accelerated cache flush | Timothy E. Hoglund, Sridhar Rao Veerla, Panthini Pandit, Gowrisankar Radhakrishnan | 2019-05-07 |
| 10223009 | Method and system for efficient cache buffering supporting variable stripe sizes to enable hardware acceleration | Timothy E. Hoglund, Sridhar Rao Veerla, Panthini Pandit, Gowrisankar Radhakrishnan | 2019-03-05 |
| 10169232 | Associative and atomic write-back caching system and method for storage subsystem | Balakrishnan Sundararaman, Shashank Nemawarkar, Larry Stephen King, Mark Ish, Shailendra Aulakh | 2019-01-01 |